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AR# 15500

LogiCORE SPI-4.2 (POS-PHY L4) - How do I skew TSClk by 180 degrees in the DCM?

Description

Keywords: PL4, TSCLK, DCM, UCF, static, alignment, phase, shift, status, channel

This Answer Record contains instructions on editing the PL4 UCF file so that the TSClk is skewed by 180 degrees in the DCM. This Answer Record applies only to Virtex-4 and Virtex-5. Please refer to the latest SPI-4.2 User Guide for information on editing the phase shift for Virtex-6 MMCMs.

Why is this work-around necessary?
This solution is presented in response to a case in which Figure 6.15 of SPI4-2 specification was misinterpreted by a user. The issue relates to the Reference Points for FIFO Status Channel Timing Parameters. The specifications state that the output of the RStat should change at the rising edge of the RSClk, and that when it reaches the input of the source core, TStat should be sampled at the rising edge of the TSClk but should meet (tS) setup time and (tH) hold time. As a result, care must be given to board layout so that tS and tH are met.

However, if the board has been laid out in such a way that TStat and TSClk reach the source core input without any skew, you can use the following work-around to skew the TSClk by 180 degrees, which should be ensure that tS and tH are met.

The Xilinx PL4 Sink Core contains an option to skew RSClk by 180 degrees. (In the POS PHY L4 GUI, look for the "RStat Changes On Falling RSClk" option.) The Xilinx PL4 Source Core GUI does not include this option; therefore, the following work-around is suggested.

Solution

If you are using SPI-4.2 version v6.0 or newer:

Edit the "pl4_wrapper.ucf" file generated by the CORE Generator and un-comment out the two lines
highlighted in bold:

###########################################################################
# TSClk DCM Phase Shift
# The PHASE SHIFT of the TSCLK DCM can be modified to change the
# alignment of TSClk relative to the TStat input. Un-comment the following
# section to skew TSClk input to 180 degrees.
# NOTE: The instance name may require modification to reflect your
# design hierarchy and synthesis tools.
######################################################################
#INST "pl4_src_top0/pl4_src_clk0/TSClkFullRate.tsclk_dcm0" CLKOUT_PHASE_SHIFT = FIXED;

# For information on selecting the ideal phase shift value for TSClk,
# please see (Xilinx Answer 15500).

#INST "pl4_src_top0/pl4_src_clk0/TSClkFullRate.tsclk_dcm0" PHASE_SHIFT = 128;

If you are using an SPI-4.2 version earlier than v6.0, you must manually add the constraints to your UCF. Using any text editor, open the "pl4_wrapper.ucf" file generated by CORE Generator. (This will be in your project directory.) Add the following statements to the source section of the UCF file:

INST "pl4_src_top0/pl4_src_clk0/tsclk_dcm0" CLKOUT_PHASE_SHIFT = FIXED;
INST "pl4_src_top0/pl4_src_clk0/tsclk_dcm0" PHASE_SHIFT = 128;

Note that the example above is for the v5.0 PL4 release. If you are using a different version of the core, the hierarchy and instance name of the TSClk DCM might be different. (In this example, the "pl4_src_top0/pl4_src_clk0/tsclk_dcm0" is the hierarchy and instance name of the TSClk DCM.)

It has been verified that the above change results in the internal TSClk of the back-annotated timing simulation file being skewed by 180 degrees. As a result, if the TStat changes approximately at the rising edge of the TSClk clock when it enters the core, TStat will be sampled internally at the falling edge of the incoming TSClk clock.
AR# 15500
Date Created 09/03/2007
Last Updated 06/20/2009
Status Active
Type General Article