UPGRADE YOUR BROWSER

We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

AR# 15504

5.1i HDL Bencher - I cannot deselect "Clock Selection" for a multiple clock design. An error reports: "variable_list_head not cleared after reorder list"

Description

Keywords: Bencher, HDLBencher, multiple, clock, selection, back, association, variable_list_head, reorder

Urgency: Standard

General Description:
I create a new source (test bench waveform) and select multiple clocks. In the next window that appears, I accidentally select an arbitrary signal as a clock. After I select "Next", I realize that the signal I selected to be a clock is incorrect.

Even though I can select the "Back" button and deselect the incorrect signal, the signal is not removed from the clock list; therefore, I cannot associate the signal with the proper clock.

When I select "Finish", a System Error [64] message reports "Variable_list_head not cleared after reorder list". When I click on "OK", another System Error [64] box reports "Variable_list_tail not cleared after reorder list".

HDL Bencher will then list the incorrect signal as a clock.

Solution

The only way to solve this problem is to close HDL Bencher and start over.

This problem is fixed in the latest 5.1i Service Pack, available at:
http://support.xilinx.com/support/techsup/sw_updates
The first service pack containing the fix is 5.1i Service Pack 1.
AR# 15504
Date Created 08/28/2002
Last Updated 02/07/2006
Status Archive
Type General Article