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AR# 15533

SYNPLIFY 7.x - "ERROR:LIT - BREFCLK or BREFCLK2 pin of GT symbol "instance_name" cannot be connected to constant."

Description

Keywords: Synplify, GT, Virtex, II, 2, Pro, processor, giga, bit, transceiver

Urgency: Hot

General Description:
When I use GT_comps in the Virtex-II Pro chip, the following error is reported after MAP runs:

"ERROR:LIT - BREFCLK or BREFCLK2 pin of GT symbol "instance_name" cannot be connected to constant."

Solution

1

Synplify is grounding the unused BREFCLK pins. To work around this problem, follow these steps:

Verilog

1. Copy the virtex2p.v into your project directory from the C:\synplicity\Synplify\lib\xilinx directory.
2. Edit the virtex2p.v file, adding the synthesis directives:

//synthesis translate_off
//synthesis translate_on

around either the BREFCLK or BREFCLK2 ports (whichever port is not being used) on the appropriate modules.
3. Add the modified virtex2p.v file to your Synplify project.
4. Remove any `include statements to the original, unmodified virtex2p.v.
5. Edit your source code and add the synthesis directives:

//synthesis translate_off
//synthesis translate_on

around either the BREFCLK or BREFCLK2 ports (whichever port is not being used) on the appropriate instantiations.

(NOTE: The synthesis directives are used to keep the source code consistent with the UniSim models.)

2

VHDL:

1. Add the synthesis directives:

--synthesis translate_off
--synthesis translate_on

around either the BREFCLK or BREFCLK2 ports (whichever port is not being used) on the appropriate component declarations and instantiations.
2. In the port-mapping, tie the unused BREFCLK port to ground. As this port will not be synthesized by Synplify, no error messages will appear during implementation. (ModelSim requires that these ports be grounded.)
AR# 15533
Date Created 09/03/2002
Last Updated 04/24/2007
Status Archive
Type General Article