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AR# 15543

4.2i ECS - Can mode pins and other configuration pins be accessed for XC4000 designs?

Description

Keywords: mode, pin, ECS, MD0, MD1, MD2, M0, M1, M2, TDO, TDO, TCK, TMS, special, function, configuration, 4000, 4K, XC4000E, XC4000L, XC4000XL, pad, I/O, IO, input, output, dedicated

Urgency: Standard

General Description:
When configuration has completed, a number of configuration pins (including MD0, MD1, MD2, TDO, TDI, TCK, and TMS) may be used as design inputs or outputs. (Please see the libraries guide for information on possible usage).

In 4.2i ECS, no PAD components exist that allow me to use configuration pins during standard user mode. As these specialty PAD components are not available in ECS, is it possible to configure these pins as user I/O during normal operation?

Solution

1

There is no option in ECS that allows the use of these specialty pins. However, you may add this functionality by editing the intermediate HDL file (.vhf or .vf) as follows:

- First, place the appropriate IBUF or OBUF on the schematic nets that will use the specialty pin(S).

- Create and view the intermediate HDL file by selecting the process "View VHDL Functional Model" (or "View Verilog Functional Model") under "Design Entry Utilities". (To edit the file, use the File -> Open option.)

- Make the following two changes to this file:

1. Change the desired port to a signal (wire).
2. Add the desired PAD component.

(The following two solutions present "before" and "after" HDL examples of a simple design.)

- Edit the file and select the "Synthesis" process. As long as the schematic has not changed, the intermediate HDL file will not be overwritten.

Please note that pin location constraints should not be used for assigning a signal to a special function pin.

2

This example illustrates a simple ECS design wherein two inputs and an output are edited in the Functional VHDL model to use the M0, M1, and M2 pins.

Before edits:
-- VHDL model created from schematic md120.sch - Wed Sep 04 16:57:57 2002

LIBRARY ieee;
LIBRARY UNISIM;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
USE UNISIM.Vcomponents.ALL;

ENTITY md120 IS
PORT ( in1 : IN STD_LOGIC;
in2 : IN STD_LOGIC;
in3 : IN STD_LOGIC;
out1 : OUT STD_LOGIC;
out2 : OUT STD_LOGIC);

end md120;

ARCHITECTURE SCHEMATIC OF md120 IS
SIGNAL a : STD_LOGIC;
SIGNAL b : STD_LOGIC;
SIGNAL c : STD_LOGIC;

ATTRIBUTE fpga_dont_touch : STRING ;
ATTRIBUTE fpga_dont_touch OF XLXI_9 : LABEL IS "true";
ATTRIBUTE fpga_dont_touch OF XLXI_5 : LABEL IS "true";
ATTRIBUTE fpga_dont_touch OF XLXI_6 : LABEL IS "true";
ATTRIBUTE fpga_dont_touch OF XLXI_7 : LABEL IS "true";
ATTRIBUTE fpga_dont_touch OF XLXI_8 : LABEL IS "true";

BEGIN
XLXI_9 : AND2 PORT MAP (I0=>b, I1=>a, O=>c);
XLXI_5 : BUF PORT MAP (I=>in3, O=>out2);
XLXI_6 : IBUF PORT MAP (I=>in1, O=>a);
XLXI_7 : IBUF PORT MAP (I=>in2, O=>b);
XLXI_8 : OBUF PORT MAP (I=>c, O=>out1);
END SCHEMATIC;


After Edits:
-- VHDL model created from schematic md120.sch - Wed Sep 04 16:57:57 2002 with minor edit of mode pins

LIBRARY ieee;
LIBRARY UNISIM;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
USE UNISIM.Vcomponents.ALL;

ENTITY md120 IS
PORT ( in3 : IN STD_LOGIC;
out2 : OUT STD_LOGIC);
end md120;

ARCHITECTURE SCHEMATIC OF md120 IS
SIGNAL a : STD_LOGIC;
SIGNAL b : STD_LOGIC;
SIGNAL c : STD_LOGIC;
SIGNAL in1 : STD_LOGIC;
SIGNAL in2 : STD_LOGIC;
SIGNAL out1 : STD_LOGIC;

ATTRIBUTE fpga_dont_touch : STRING ;
ATTRIBUTE fpga_dont_touch OF XLXI_9 : LABEL IS "true";
ATTRIBUTE fpga_dont_touch OF XLXI_5 : LABEL IS "true";
ATTRIBUTE fpga_dont_touch OF XLXI_6 : LABEL IS "true";
ATTRIBUTE fpga_dont_touch OF XLXI_7 : LABEL IS "true";
ATTRIBUTE fpga_dont_touch OF XLXI_8 : LABEL IS "true";

BEGIN
XLXI_9 : AND2 PORT MAP (I0=>b, I1=>a, O=>c);
XLXI_5 : BUF PORT MAP (I=>in3, O=>out2);
XLXI_6 : IBUF PORT MAP (I=>in1, O=>a);
XLXI_7 : IBUF PORT MAP (I=>in2, O=>b);
XLXI_8 : OBUF PORT MAP (I=>c, O=>out1);

U1: MD0 port map ( I => in1);
U3: MD2 port map ( I => in2 );
U5: MD1 port map ( O => out1);

END SCHEMATIC;

3

This example illustrates a simple ECS design wherein two inputs and an output are edited in the Functional Verilog model to use the M0, M1, and M2 pins.

Before edits:
// Verilog model created from schematic md120.sch - Thu Sep 05 09:53:09 2002

`timescale 1ns / 1ps

module md120(in1, in2, in3, out1, out2);

input in1;
input in2;
input in3;
output out1;
output out2;

wire a;
wire b;
wire c;

AND2 XLXI_9 (.I0(b), .I1(a), .O(c));
/* synopsys attribute fpga_dont_touch "true"*/
BUF XLXI_5 (.I(in3), .O(out2));
/* synopsys attribute fpga_dont_touch "true"*/
IBUF XLXI_6 (.I(in1), .O(a));
/* synopsys attribute fpga_dont_touch "true"*/
IBUF XLXI_7 (.I(in2), .O(b));
/* synopsys attribute fpga_dont_touch "true"*/
OBUF XLXI_8 (.I(c), .O(out1));
/* synopsys attribute fpga_dont_touch "true"*/
endmodule


After Edits:
// Verilog model created from schematic md120.sch - Thu Sep 05 09:53:09 2002 with minor edit of mode pins

`timescale 1ns / 1ps

module md120(in3, out2);

input in3;
output out2;

wire a;
wire b;
wire c;
wire in1;
wire in2;
wire out1;

AND2 XLXI_9 (.I0(b), .I1(a), .O(c));
/* synopsys attribute fpga_dont_touch "true"*/
BUF XLXI_5 (.I(in3), .O(out2));
/* synopsys attribute fpga_dont_touch "true"*/
IBUF XLXI_6 (.I(in1), .O(a));
/* synopsys attribute fpga_dont_touch "true"*/
IBUF XLXI_7 (.I(in2), .O(b));
/* synopsys attribute fpga_dont_touch "true"*/
OBUF XLXI_8 (.I(c), .O(out1));
/* synopsys attribute fpga_dont_touch "true"*/
MD0 U1 (.I(in1));
MD2 U2 (.I(in2));
MD1 U3 (.O(out1));

endmodule
AR# 15543
Date Created 09/04/2002
Last Updated 08/12/2003
Status Archive
Type General Article