When I simulate a POS PHY L4 core using NC-Verilog (by Cadence) or VCS (by Synopsys), unusual and inconsistent behaviors occur. Behaviors include:
- Packets being dropped.
- SnkFFErr being asserted.
- Packets being issued to the user/FIFO interface without SOP (i.e., SnkFFSOP is being dropped).
- SnkFFData bytes being swapped.
- An error being reported on every other training pattern.
This problem may not be limited to NC-Verilog and VCS. It could occur on other simulators as well.
When a PL4 core is simulated in Verilog, race conditions that show the above behaviors can occur. You may avoid the failures above by not using the following simulator switches (options):
For NC-Verilog (Cadence), simulate without:
+delay_mode_distributed
+noneg_tchks
For VCS (Synopsys), simulate without:
+no_specify