UPGRADE YOUR BROWSER

We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

AR# 15586

5.2i XST - Creating Finite State Machines (FSMs) with XST

Description

Keywords: FSM, finite, state, machine, Verilog, VHDL, XST

Urgency: Standard

General Description:
XST will synthesize HDL as normal code and not FSM code when the following conditions exist:

- The FSM has a constant that is greater than 32 bits
- The FSM has a clock enable on the state registers
- The FSM does not have a reset

Any of the conditions above will cause XST to ignore any FSM directive (internal FSM extraction algorithms, state encoding type, etc.)

Solution

If you wish to use the XST directives that are available for FSMs, avoid the above conditions so that XST will recognize the HDL as FSM code.
AR# 15586
Date Created 09/11/2002
Last Updated 10/20/2005
Status Archive
Type General Article