UPGRADE YOUR BROWSER

We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

AR# 15650

LogiCORE PCI - An address stepping bit in the command register is set to "0" as of PCI Spec Rev 2.3

Description

General Description:

When I use PCI LogiCORE and read from the command register before any changes are made, the command register returns "0x0000". (This occurs as of release version 3.100 of the core.) Previous versions read back "0x0080". The change affects Bit 7, which describes whether or not the interface supports address stepping.

Why did this change?

Solution

Prior to PCI Specification Rev 2.3, this bit was set to "1" if the device used address stepping. The rules for address stepping changed in PCI Spec Rev 2.3, and this bit should no longer be set.

However, the core operation has not changed because Rev 2.3 of the specification still allows for 3-state buffers to be turned on one cycle early. The core has always functioned this way, but this is no longer a reason to set the address stepping bit as described in PCI Spec Rev 2.3 section 3.6.3.

Please see (Xilinx Answer 12826) for further details on how the Xilinx PCI LogiCORE performs address stepping.

AR# 15650
Date Created 09/03/2007
Last Updated 12/15/2012
Status Active
Type General Article