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AR# 15685

6.1 System Generator for DSP - Decimation filters with a down sampling of "2" and symmetry in the impulse response fail in core generation

Description

General Description:

If a decimation filter is used with a down sampling of "2" and symmetry in the impulse response, an internal error occurs when my design is generated. The "coregen.log" file reports the following error:

"GENERATE

# Preparing to elaborate core...

# Elaborating the module...

# ERROR: An internal error has occurred. To resolve this error, please consult the Answers Database at http://support.xilinx.com
# ERROR: Sim has a problem implementing the selected core. Implementation netlist will not be generated.

# ERROR: SimGenerator: Failure of Sim to implement customization parameters core filter_simulation_xlfir_1ch_core2

# ERROR: Did not generate EDIF implementation netlist (.EDN) file for core <filter_simulation_xlfir_1ch_core2>.

# Generating the .VEO/.V simulation support files...

# WARNING: Warnings and/or errors encountered while generating filter_simulation_xlfir_1ch_core2 (Distributed Arithmetic FIR Filter 6.0) Not all output products were generated successfully.

#

# ERROR: Errors occurred at line 46. GENERATE

# ERROR: Errors found during execution of command file sysgen.sgxco"

Solution

This problem is caused by a bug in the DA FIR v.6 of the core that affects decimation by "2" with symmetry. This problem will be fixed in the next release of the System Generator for DSP.

Meanwhile, you can work around this issue in the following two ways:

Work-around 1

Explicitly direct the filter block to not use symmetry. This will slightly affect the size of your design, but not by much because there are only symmetric pairs in decimation polyphase filters and not true symmetry. In fact, when non-symmetry is used for certain designs, the hardware over-sampling rate may increase because the pre-adder required for symmetry optimization is not used, and this saves logic and counter balances the increase in size.

For more information on hardware over-sampling, please see (Xilinx Answer 15686).

Work-around 2

Perform the following steps:

1. De-select the "Generate Core" check box in the GUI and run the code generation completely.

2. In CORE Generator, generate the DA FIR filter core separately using Version 7. (The problem is fixed in Version 7.)

3. Add this core to the System Generator project files.

AR# 15685
Date Created 09/03/2007
Last Updated 12/15/2012
Status Active
Type General Article