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AR# 15691

Functional Simulation, VHDL, ModelSim - "ERROR: Formal status must not be associated with OPEN when sub-elements are associated individually"

Description

Keywords: Functional, Simulation, ModelSim, Formal, Status, associated, OPEN, subelements, individually, ECS

Urgency: Standard

General Description:
When the Status pins of the DCM are used, the component declaration must declare the Status as an 8-bit vector in order to match the behavioral model. When only the Status 1 or Status 2 outputs are used, the other ports must be left unconnected. If they are associated with "open" in the port map (STATUS(0)=>open), the following error occurs in ModelSim:

"# ERROR: xxx.vhd(xxx): Formal status must not be associated with OPEN when sub-elements are associated individually."

Solution

1

This problem was fixed in ISE 6.3i.

An alternate way to work around this issue is as follows:

To avoid any errors or warnings, connect the unused Status outputs to unconnected signals. The signal declarations and a snippet of the port map are below:

(NOTE: This change is performed in the ".vhf" file, which is the equivalent VHDL file written out by ECS.)

-- Signal declarations for dummy signals

SIGNAL STATUS7_unconnected : STD_LOGIC;
SIGNAL STATUS6_unconnected : STD_LOGIC;
SIGNAL STATUS5_unconnected : STD_LOGIC;
SIGNAL STATUS4_unconnected : STD_LOGIC;
SIGNAL STATUS3_unconnected : STD_LOGIC;
SIGNAL STATUS0_unconnected : STD_LOGIC;

-- Snippet of the port map for the DCM

STATUS(7)=>STATUS7_unconnected,
STATUS(6)=>STATUS6_unconnected,
STATUS(5)=>STATUS5_unconnected,
STATUS(4)=>STATUS4_unconnected,
STATUS(3)=>STATUS3_unconnected,
STATUS(2)=>STATUS(2),
STATUS(1)=> STATUS(1),
STATUS(0)=>STATUS0_unconnected);

2

If the -87 switch is used instead of the -93 switch in the VSIM command line, the error will become a warning and the simulation will proceed.
AR# 15691
Date Created 09/03/2007
Last Updated 11/18/2008
Status Archive
Type General Article