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AR# 1579

FPGA Configuration - Size of external pull-down needed to create a logic Low.

Description

It may be necessary at times to attach an external pull-down resistor to an FPGA user I/O to counter the internal pull-up resistor and ensure a logic Low signal during configuation (internal pull-up is active). What size pull-down is necessary to ensure a logic Low?

Solution

For MODE pins, a maximum resistance of 2.7 kilohms is recommended. For I/Os, there may be other considerations for the application. A typical value is 3.3 kilohms as shown below.

Given that the minimum impedence of an internal pull-up resistor for the xc5200 and xc4000 families is stated to be

20 kilohms, Vcc=5V, and V(IL) Max=0.8V.

A simple voltage-division equation reveals:

V1 = V(R1/(R1+R2))

which is

0.8 = 5(R1/(R1+20000)

and results in

R1=3.8 kilohms

An external pulldown resistor impedence of 3.8 kilohms or less should ensure a logic low during configuration.

AR# 1579
Date Created 08/21/2007
Last Updated 12/15/2012
Status Active
Type General Article