AR #15814 - 5.1i ECS - During a schematic check, "no load" and "no source" errors are reported when the driven net is part of a complex bus
5.1i ECS - During a schematic check, "no load" and "no source" errors are reported when the driven net is part of a complex bus
| AR# | 15814 |
| Part | Schematic Editor |
| Last Modified | 2006-01-09 00:00:00.0 |
| Status | Archive |
| Keywords | complex, CAT, concatenated, compound, bus, ECS, no load, no source, ISE, WebPACK |
Description
Keywords: complex, CAT, concatenated, compound, bus, ECS, no load, no source, ISE, WebPACK
Urgency: Standard
General Description:
When I perform a schematic check, CAT buses or complex buses containing bus notation such as "mybus(3:0)" report "no load" and "no source" errors.
For example, suppose a design contains two particular inputs, "mybus(6:0)" and "mybit". An 8-bit input pin is driven by a complex bus called "mybus(6:0),mybit". The schematic check will produce the following errors:
"Error: Bus 'mybus(6:0)'is connected to a source pin and/or I/O Ports while there is no load pin or I/O port connected to it.
Error: Net 'mybus(6)'is connected to load pins and/or I/O Ports, but there is no source pin or I/O port connected to it.
Error: Net 'mybus(5)'is connected to load pins and/or I/O Ports, but there is no source pin or I/O port connected to it.
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Error: Net 'mybus(0)'is connected to load pins and/or I/O Ports, but there is no source pin or I/O port connected to it."
Solution
You may work around this problem in two ways:1. Add a wire segment, naming it using any portion of the bus name (i.e., mybus(1:0)).
2. In ECS, select Edit -> Preferences. Under "Schematic Editor/Check", change the "Consider Loadless Net as" and "Consider Undriven Net as" fields to "Warning" rather than "Error".
Then, when the schematic check is run, the warnings will still appear, but the HDL will be created correctly and the design will implement.
NOTE: If portions of the bus are intentionally not driving any load and you would like to avoid the warning/error messages, you can:
1. Connect the input of a BUF element to the bus
2. Change the name of the BUF to match the bus size (i.e. Change the instname from XLXI_5 to mybuf(3:0) to connect to a 4 bit bus)
The output of the BUF may be left hanging.
This problem is fixed in the latest 5.1i Service Pack, available at:
http://support.xilinx.com/support/techsup/sw_updates
The first service pack containing the fix is 5.1i Service Pack 3.