UPGRADE YOUR BROWSER

We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

AR# 15894

LogiCORE RapidIO - Why is LNK_TDST_RDY_N asserted before the PHY has trained?

Description

Why is LNK_TDST_RDY_N asserted before the PHYS has trained? Shouldn't the buffer be prohibited from sending data when LNK_TRDY_N is not asserted?

Solution

When the PHY comes out of reset, it can accept data from the buffer even though it has not trained. This is because the PHY contains FIFOs that can be loaded with data. If data is placed into the buffer, the buffer will begin to send data to the PHY and LNK_TDST_RDY_N will go High after the FIFO starts filling up. Once the PHY has trained, it will send the data over the link and re-assert LNK_TDST_RDY_N to the buffer so that more data can be transferred to the PHY.
AR# 15894
Date Created 09/03/2007
Last Updated 05/15/2014
Status Archive
Type General Article