We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

AR# 15898

5.1i Virtex-II PAR - "ERROR:Place:249 - Automatic clock placement failed..."


Keywords: ERROR:Place:249, automatic, clock, placement

Urgency: Standard

General Description:
A design that ran through PAR successfully in the 4.2i software fails in the 5.1i placer during Phase 4.2, reporting the following error:

"ERROR:Place:249 - Automatic clock placement failed. Please attempt to analyze the global clocking required for this design and either lock the clock placement or area locate the logic driven by the clocks so that the clocks may be placed in such a way that all logic driven by them may be routed. The main restriction on clock placement is that only one clock output signal for any Primary/Secondary pair of clocks may enter any region. For further information, see the "Global clocks" section in the Virtex-II Platform FPGA User Guide ("Design Considerations" section) at:"


This error is usually due to a problem with LOCs or area constraints that are applied to macros so they cannot be placed within a single clock region. It can also occur without constraints if the macro is taller than any clock region.

This issue will be fixed in 5.1i Service Pack 3, which will be available in mid-December, 2002. Meanwhile, you can work around the problem by setting the following environment variable:



This work-around only works if all clock logic (BUFGMUXs, DCMs) is LOC'd and all clock domains are area-constrained so that no primary/secondary BUFGMUX pairs drive logic in the same clock region. Otherwise, some clock routing may not be able to use the global resources.

A clock region is a subset of a quadrant. The number and size of clock regions varies with the size of the part. The number varies from 4 to 16, and the size varies from 8 to 16 CLB rows. The width is always one half of the device.
AR# 15898
Date Created 09/03/2007
Last Updated 10/19/2008
Status Archive
Type General Article