When I simulate my System Generator design, the following error is reported:
"Error reported by S-function 'xldelay' in block 'example3/Delay2':
--- Unconnected Input Port.
All input ports on Xilinx blocks must be connected before simulating, compiling, or netlisting the design."
However, all the blocks referenced by the error are connected correctly. Connecting non-Xilinx blocks to Xilinx blocks without the correct use of gateway blocks can also cause this error.
This error refers to a problem with sample time and data type propagation in Simulink. Generally, designs exhibiting these problems have feedback loops that can create problems for the propagation rules if care is not exercised. The following rules of propagation help establish some "Dos and Don'ts" for feedback loop design.
Sample Time and Data Type Propagation
All System Generator designs use sample times to determine how often each block is executed, and to determine the particular data format needed (signed, unsigned, a particular width, and a correctly-placed decimal point). To maintain design flexibility and usability, only two types of blocks must have their "Sample Period" and "Data Type Format" explicitly set:
- Gateway In blocks
- Blocks that do not have inputs (e.g., Counters, DDS)
All other blocks inherit sample periods and data types from their inputs.
However, there are caveats to this problem, especially concerning feedback loops, which are common in DSP applications. The diagram below illustrates a feedback system. The adder in this system has two inputs -- the sample period for this block is determined from the sample period of both inputs; if these periods are not the same, an error occurs.
As the "b" input's sample period cannot yet be determined because it is in a feedback loop, the tools fails to propagate the sample period for the design, and the misleading error message is displayed. In this example, the problem is resolved by explicitly setting the sample time to "-1". This is called "explicitly inherited", which means that the first known input is used as the sample period for this block.
Please note that in the system above, the adder should not be set to full precision because this creates an algebraic loop that causes the tools to report an error.
The next diagram shows a similar feedback example with problems that may also cause the "Unconnected Input Port" error. The system is a 1-bit counter system and illustrates how data type propagation must often be explicitly set. In this example, the desired bus width is "1", but since there is no input to the loop, the system does not receive the data bit width information. To solve this problem, you must use the "Convert" block to specify to the loop the sample period and data type format required for this system.
In summary, to avoid the misleading "Unconnected Input Port" errors, follow these "Dos and Don'ts" regarding the basic rules for feedback loops:
1. Be sure to use the explicitly inherited operator (-1) in feedback loops that have inputs from other parts of your design to ensure that the first known sample period is inherited.
2. Explicitly set the same period on a block in a loop if there are no inputs into the feedback loop.
3. Use the "Convert" (or "Slice and Re-interpret") block to avoid algebraic loops, and explicitly set the data type format for the feedback loop. (The user-defined precision on arithmetic blocks can be used as well.)