When I run a design through the 5.1i software that was also run through the 4.2i software, the logic levels reported in the 5.1i timing report are different. (Figures 2 and 3 below are examples of the 4.2i and 5.1i timing reports, respectively).
I have not modified the design -- what is happening to the levels of logic in the new timing report?
The algorithm that accounts for the logic levels of the data path delay in TRCE was changed in the 5.1i software. The Clock-to-Out delay (Tcko) is no longer counted as one level of logic. Additionally, the setup to a flip-flop (i.e., Tdyck or Tdxck) should not be counted as one level of logic unless the BEL primitive of the destination is associated with either a LUT or a MEM. Moreover, if the path goes through a RESET pin, it will not be counted as a level of logic.
Suppose that the cloud of logic between the source and data registers contains N levels of logic. In version 4.2i, the TRCE algorithm reports N+2 levels of logic for the entire data path delay. In version 5.1i, TRCE only reports N levels of logic for the entire data path delay.
For example, assume that the red box in "Figure 1 - Timing Path Design Example" is the cloud of logic, which contains only one level of logic (N = 1).
In the 4.2i software, Data Path Delay levels of logic will report three levels of logic (N+2 = 1+2 = 3), as illustrated in "Figure 2 - 4.2i Timing Report Showing Levels of Logic":
The Data Path Delay levels of logic reported in version 5.1i will only report one level of logic, as illustrated in "Figure 3 - 5.1i Timing Report Showing Levels of Logic":