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AR# 15955

LogiCORE SPI-4.2 (POS-PHY L4) v5.0 - RSClk is shifted with respect to RStat and the RSClkPhase control signal is ignored


General Description:

In the v5.0 PL4 core, the RSClkPhase static configuration signal sets the relationship between RSClk and RStat. However, this does not currently work under all conditions, and RSClk may be shifted by 90 or even 180 degrees, regardless of the RSClkPhase setting.

The occurrence of this problem depends on when SnkEn is released -- the relationship between RSClk and RStat depends on the time that SnkEn is asserted. This causes the phase relationship between RSClk and RStat to be unpredictable, regardless of the RSClkPhase or RSClkDiv value that you have selected.


This problem is fixed in the SPI-4.2 (POS-PHY Level 4) core v5.1 and later.

AR# 15955
Date 05/03/2010
Status Archive
Type General Article