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AR# 15974

5.1i ECS - When I implement a schematic design, MAP reports: "ERROR:Pack:679 - Unable to obey design constraints..."

Description

Keywords: ECS, multiple, instances, MAP, pack, hierarchy, U_SET, H_SET, HU_SET, ISE, symbol, instance, RLOC, RPM, component, attribute, slice, XGROUP, macroname

Urgency: Hot

General Description:
MAP fails if my ECS schematic design includes two instances of a user-created macro that contains Xilinx RPM macros.

For example:

1. I create a macro named "my_counter".
2. The "my_counter" macro contains a Xilinx library component named "cc8ce."
3. The "cc8ce" component is an RPM macro and contains RLOC constraints for placing registers in a specific physical order.
4. My top-level design contains two or more instances of "my_counter."

MAP fails and reports eight errors (one for each FF) similar to the following:

"ERROR:Pack:679 - Unable to obey design constraints (MACRONAME=I_Q0_0, RLOC=R0C0.S0), which require the combination of the following symbols into a single SLICE component:

FLOP symbol "xlxi_37/xlxi_1/i_q0/i_36_35" (Output Signal = xlxi_37/xlxi_1/q0)
FLOP symbol "xlxi_29/xlxi_1/i_q0/i_36_35" (Output Signal = xlxi_29/xlxn_1)
FLOP symbol "xlxi_37/xlxi_2/i_q0/i_36_35" (Output Signal = xlxi_37/xlxi_2/q0)
FLOP symbol "xlxi_37/xlxi_3/i_q0/i_36_35" (Output Signal = xlxi_37/xlxi_3/q0)
FLOP symbol "xlxi_37/xlxi_4/i_q0/i_36_35" (Output Signal = xlxi_37/xlxi_4/q0)
FLOP symbol "xlxi_45/i_q0/i_36_35" (Output Signal = vida0_obuf)
FLOP symbol "xlxi_37/xlxi_8/i_q0/i_36_35" (Output Signal = xlxi_37/xlxi_8/q0)"

"ERROR:Pack:679 - Unable to obey design constraints (MACRONAME=I_Q0_0, RLOC=R0C0.S0), which require the combination of the following symbols into a single SLICE component:
.
.
.
Symbols have different XGROUP parameters. Please correct the design constraints accordingly. Problem encountered during the packing phase.

Design Summary
--------------
Number of errors: 8
Number of warnings: 0
ERROR: MAP failed"

Solution

This problem is fixed in the latest 5.2i ISE software.

This problem occurs because ECS 5.1i places a U_SET attribute on every instance of a Xilinx component containing RLOCs. The U_SET is given a different value depending upon the instance name. However, since the U_SET attribute is not limited to hierarchical boundaries, if a macro with such an instance is used more than once, then conflicts occur within the user set defined by the U_SET attribute.

In ECS 5.2i, the U_SET attributes are replaced by H_SET attributes that are defined by hierarchical boundaries.

To work around this problem with the 5.1i software, perform the following steps:

1. Open each of the intermediate *.vhf or *.v files and perform a global find-and-replace of U_SET with H_SET or HU_SET.
2. Run synthesis with the "Keep Hierarchy" option selected.

This keeps the RLOC sets together but prevents the MAP conflicts because H_SET and HU_SET do not pass hierarchical boundaries.
AR# 15974
Date Created 10/23/2002
Last Updated 01/08/2006
Status Archive
Type General Article