UPGRADE YOUR BROWSER

We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

AR# 16037

5.1i Timing Simulation, Spartan-II - DLL simulation leads to "# ** Warning: */X_CLKDLL PERIOD High VIOLATION ON CLKIN;..."

Description

Keywords: DLL, CLKDLL, timing, simulation, Spartan, 6, period, High, Low, violation, CLKIN

Urgency: Standard

General Description:
When I run a timing simulation for a Spartan-II device, the following warning is reported for a DLL in the design:

"# ** Warning: */X_CLKDLL PERIOD High VIOLATION ON CLKIN;
# Expected := 11.111 ns; Observed := 10 ns; At : 602.655 ns."

These types of warnings indicate that the input period specifications stated in the data sheet have been exceeded. In most instances, the warnings are valid.

In the following circumstances, however, the warning may be incorrect:

1. When a -6 speed grade is used for a Spartan-II device;
2. When a CLKDLL is used in low-frequency mode and the input clock frequency is over 90MHz and under 100MHz;
3. When a CLKDLL in high-frequency mode and the input clock frequency is over 180MHz and under 200MHz.

In these cases, the warnings are not valid because the speed files incorrectly use the maximum frequency values for the -5 speed grade for both the -5 and the -6 speed grades.

Solution

1

These warnings can be safely ignored, as they do not affect the simulation.

This issue will be fixed in the 5.2i software release, which will be available in late February, 2003.

2

If these warnings cannot be ignored, you can modify the SDF. We do not generally recommended the modification of any Xilinx-generated files, but this method can be used if ignoring the warnings is not an acceptable work-around.

To edit the SDF, follow the instructions below:

- Open the SDF file and search for instance X_CLKDLL. You will see:

(CELL (CELLTYPE "X_CLKDLL")
(INSTANCE u2)
(DELAY
(ABSOLUTE
(PORT RST (1163:1163:1163)(1163:1163:1163))
(PORT CLKFB (995:995:995)(995:995:995))
(PORT CLKIN (6:6:6)(6:6:6))
(IOPATH CLKIN LOCKED (1177:1177:1177)(1177:1177:1177))
)
)
(TIMINGCHECK
(WIDTH (posedge RST) (3000:3000:3000))
(WIDTH (posedge CLKIN) (3000:3000:3000))
(WIDTH (negedge CLKIN) (3000:3000:3000))
(PERIOD (posedge CLKIN) (11111:11111:11111))
)
)

- Change the value of PERIOD to:

(CELL (CELLTYPE "X_CLKDLL")
(INSTANCE u2)
(DELAY
(ABSOLUTE
(PORT RST (1163:1163:1163)(1163:1163:1163))
(PORT CLKFB (995:995:995)(995:995:995))
(PORT CLKIN (6:6:6)(6:6:6))
(IOPATH CLKIN LOCKED (1177:1177:1177)(1177:1177:1177))
)
)
(TIMINGCHECK
(WIDTH (posedge RST) (3000:3000:3000))
(WIDTH (posedge CLKIN) (3000:3000:3000))
(WIDTH (negedge CLKIN) (3000:3000:3000))
(PERIOD (posedge CLKIN) (10000:10000:10000))
)
)

NOTE: This change is strictly for the -6 speed grade when the CLKDLL is used in low-frequency mode. If you are using the CLKDLL in high- frequency mode and are using the -6 speed grade, the PERIOD will be 5555 and can be changed to 5000.
AR# 16037
Date Created 09/03/2007
Last Updated 11/18/2008
Status Archive
Type General Article