UPGRADE YOUR BROWSER

We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

AR# 16052

5.1isp2 Timing Analyzer/Trace(TRCE) - A negative Tdcmino value causes hold errors in timing for the PSDONE path

Description

General Description:

A hold error appears in my timing report on the PSDONE path from the DCM to a register.

Solution

This error occurs because the PSDONE path is associated with the wrong timing parameter (Tdcmino). You can work around this problem by applying a TIG constraint on the net from PSDONE to the register.

This problem is fixed in the latest 5.1i Service Pack, available at:

http://support.xilinx.com/support/techsup/sw_updates
The first service pack containing the fix is 5.1i Service Pack 3.

AR# 16052
Date Created 09/03/2007
Last Updated 01/18/2010
Status Archive
Type General Article