The SPI4.2 (PL4) Core performs static alignment by using the RDClk DCM to shift the internal version of the RDClk such that its edges are centered on the data eye (RDat/RCtl) at the IOB DDR flip-flops. The ability to shift the internal clock in small increments (~50 ps) is critical for sampling high-speed source synchronous signals such as SPI4.2. For statically aligned systems, the DCM output clock phase offset (as set by the phase shift value) is a critical part of the system, as is the requirement that the PCB is designed with precise delay and impedance-matching for all the differential pairs of the LVDS data bus.
You must determine the best DCM setting (phase shift) to ensure that the target system has the maximum system margin to perform across voltage, temperature, and process (multiple chips) variations. Testing the system to determine the best DCM phase shift setting has the added advantage of providing a benchmark of the system margin based on the UI (unit interval or bit time). System margin is defined as the following:
System Margin (ps) = UI(ps) * (working phase shift range/128)
This Answer Record describes how to find the ideal phase shift value for your system.
Xilinx cannot recommend a singular phase shift value that is effective across all hardware platforms. Xilinx does not recommend attempting to determine the phase shift setting empirically. In addition to the clock-to-data phase relationship, other factors such as package flight time (package skew) and clock routing delays (internal to the device) affect the clock data relationship at the sample point (in the IOB) and are difficult to characterize.
Xilinx recommends extensive investigation of the phase shift setting during hardware integration and debugging. The phase shift settings provided in SPI-4.2 constraint files is a placeholder, and works successfully on Xilinx SPI-4.2 hardware platforms. (Note that this default setting has changed for the various SPI-4.2 releases to account for issues such as changes to the DCM DESKEW ADJUST attribute.)
Perform a complete sweep of phase shift settings during your initial system test. Use only positive (0 to 255) phase shift settings, and use a test range that covers a range of no less than 128, corresponding to a total 180 degrees of clock offset. This does not imply that 128 phase shift must be tested; increments of 4 (52, 56, 60, etc.) correspond to roughly one DCM tap, and consequently provide an appropriate step size. Additionally, it is not necessary to characterize areas outside the working phase shift range.
At the edge of the operating phase shift range, system behavior changes dramatically. In eight phase shift settings or less, the system can transition from no errors to exhibiting errors (or being unable to stay in frame (SnkOof)). Checking the operational edge at a step size of two (on more than one board) refines the typical operational phase shift range. Once the range is determined, choose the average of the high and low working phase shift values as the default. During the production test, Xilinx recommends that you re-examine the working range at corner case operating conditions to determine whether any final adjustments to the final phase shift setting are needed.
You can use FPGA Editor to generate the required test file set instead of resorting to multiple PAR runs. Performing the test on design files that differ only in phase shift setting prevents other variables from affecting the test results. FPGA Editor operations can even be scripted further, reducing the effort needed to perform this characterization. Note that the sample scripts provided below must be modified to match your instance names if the instance name for the RDClk DCM or MMCM is different than used in the Example Design constraint file to LOC the RDClk DCM, apply the FIXED constraint onto the DCM, etc. These default constraints are illustrated below (where "<core_name>" is the component name entered into CORE Generator):
For Virtex-5 devices and earlier:
INST "<core_name>_pl4_snk_top0/U0/clk0/rdclk_dcm0" CLKOUT_PHASE_SHIFT = FIXED;
INST "<core_name>_pl4_snk_top0/U0/clk0/rdclk_dcm0" PHASE_SHIFT = 25;
For Virtex-6 devices:
INST "pl4_snk_clk0/mmcm0" CLKOUT0_PHASE=90;
To use this script, you must have a completely routed SPI-4.2 core design with Static Alignment. The sink core must be using a DCM or MMCM to perform phase shifting. This version of the script does not support shifting of IDELAY taps. Hence, "global clocking" must be used for sink clocking option, not "regional clocking". The following should be indicated in your SPI-4.2 ".xco" file:
These scripts were written using v9.3 of the Xilinx SPI-4.2 Core and are supported on PC, UNIX and LINUX systems. The scripts can easily be altered for a custom design or for earlier versions of the core; see the comments in the Perl script for details. The script uses the Perl executable provided with Xilinx ISE design tools.
Steps to generate multiple BIT files with different DCM or MMCM phase shift settings.
1. For all cores using Virtex-5 devices or earlier , download spi42_make_shift_v3.zip from the following FTP site:
For Virtex-6 device cores, download spi42_make_shift_virtex6.zip from the following FTP site:
2. Extract the ".zip" file into an empty directory. The ".zip" file will contain:
a. readme.txt - readme document
b. make_shift_v3.pl or make_shift_virtex6.pl - main executable script (Pearl Script)
c. fe_template_v3.scr or fe_template_virtex6.scr - template script needed by FPGA_EDITOR
d. bitgen.ut - blank bitgen option file. Even if there are no bitgen options used, a blank "bitgen.ut" is needed.
3. Copy your SPI4.2 design files into above directory. The files needed are:
a. Routed.ncd - your routed design file (must have name "routed.ncd")
b. Mapped.pcf - your pcf constraint file (must have name "mapped.pcf")
c. Bitgen.ut - your design bitgen.ut file, or if you do not have one, place the blank "bitgen.ut" provided in the zip.
4. Run make_shift_v3.pl or make_shift_virtex6.pl in a directory containing all the above files mentioned in steps 2 and 3. The script must be run from a command prompt in an environment set to run Xilinx ISE design tools.
Command_prompt> xilperl make_shift_v3.pl
The script prompts you for the following information:
- Whether you would like to keep all the NCD, PCF, and BGN files. Answering "Y" or "y" will keep all iterations (32 copies of ncd, pcf, bgn,drc) of files in your directory. Answering "N" or "n" will keep only the BIT files. It is recommended that you enter "n", unless you have had issues and need the shifted NCD files for debugging.
- For "make_shift_v3.pl" only: The component name used when generating the core. This must be the exact name used when the SPI-4.2 core was generated. This can be found in your SPI-4.2 XCO file.
(e.g., CSET component_name=pl4_v9_3)
NOTE: Entering incorrect information will result in the following error:
"ERROR:FPGAEditor:29 - Cannot find a component name ? "
Regardless of the error, the script continues to generate the NCD files and the BIT file; however, with the original PHASE SHIFT value for all the BIT files. In other words, generated BIT files will not have the appropriate phase shifting values. So, be sure to type the correct information when prompted.
The script also runs bitgen in command-line mode. Warning messages similar to the following are expected when bitgen is running:
"WARNING:PhysDesignRules:367 - The signal <pl4_v9_3_vir5_static_pl4_snk_top0/U0/io0/buffer_data/Ctl0/OB> is incomplete. The signal does not drive any load pins in the design.
WARNING:PhysDesignRules:1416 - Dangling pins on block:<pl4_v9_3_vir5_static_pl4_snk_top0/U0/io0/chan13/U1_ML_IODELAY>:<IODELAY_IODELAY>. With IDELAY_TYPE programming FIXED or DEFAULT any active input pins INC RST CE and C are not used and will be ignored."
The script outputs a "modified.scr" file which is used when FPGA Editor is run in command-line mode. This file should contain the correct component name you have entered appended to the proper instance name of the DCM embedded in SPI-4.2 core. The script also runs the bitgen command on all iterations of the NCD file and can take up to approximately 60 minutes depending on the system.
Upon completion of the script, you should have multiple BIT files with a unique phase shift value specified in the file name. Try these BIT files in your system on numerous boards. The non-working file gives you DIP4 errors within seconds. And the working BIT file runs for hours without any DIP4 error. It is critical to determine the working range of the phase shift value and use the middle of the range. Selecting only the good mid-range assures functionality of the core through power, voltage, and temperature variations.
08/23/2006 - Initial Release
10/21/2009 - Updated for "v3" and Virtex-6 scripts