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AR# 16113

5.1i ECS - Schematic check reports "no load" (DesignEntry:13) and "no source" (DesignEntry:11) errors


Keywords: undriven, vector, connected, bus, ECS, no load, no source, ISE, WebPACK, DesignEntry, port, IO, I/O

Urgency: Standard

General Description:
When I perform a schematic check in 5.1i, the system reports "no load" and "no source" errors on designs that passed without errors in the 4.2i software.

If I select, Tools -> Check Schematic, errors similar to the following are reported:

"Error: Net 'mysig' is connected to a source pin and/or I/O Ports while there is no load pin or I/O port connected to it."
"Error: Net 'mydriver' is connected to load pins and/or I/O Ports, but there is no source pin or I/O port connected to it."

When I attempt to implement the design, SCH2VHDL or SCH2VERILOG reports errors similar to the following:

"ERROR:DesignEntry:13 - Net "mysig" is connected to source pins and/or IO ports while there is no load pin connected to it."
"ERROR:DesignEntry:11 - Net "mydriver" is connected to load pins and/or IO Ports, but there is no source pin or IO Port connected to it."


In the 5.1i software release, schematic checks were added to prevent users from inadvertently leaving nets unconnected. However, in some cases, a user intentionally leaves a net unconnected to use only a portion of a macro's bus output, or to place nets in the design for future use.

These error messages can be changed to warnings as followings:

1. In ECS, select Edit -> Preferences.
2. Under "Schematic Editor/Check", change the "Consider Loadless Net as" and "Consider Undriven Net as" fields to "Warning" rather than "Error".

When the schematic check is run, the warnings will still appear, but the HDL will be created correctly, and the design will implement. In the 5.2i software, these schematic checks will be flagged as warnings by default.

NOTE: If portions of the bus are intentionally not driving any load and you would like to prevent the warnings/errors, you may:

1. Connect the input of a BUF element to the bus.
2. Change the name of the BUF to match the bus size (i.e., Change the instname from "XLXI_5" to "mybuf(3:0)" to connect to a 4-bit bus.)

The output of the BUF may be left hanging.

For more information, please see (Xilinx Answer 15814).
AR# 16113
Date Created 11/12/2002
Last Updated 01/08/2006
Status Archive
Type General Article