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AR# 16129

5.1i CORE Generator - Single-Port Block Memory v5.0: Behavioral simulation reports incorrect latency when "Additional Output Pipe Stages"=1 and "Write Mode"="No Read On Write"


General Description

When "Additional Output Pipe Stages" is set to 1 and "Write Mode" is set to "No Read On Write", the output during a write operation following a read operation will be incorrect in both the VHDL and Verilog behavioral models. Why does this occur?


This problem has existed since version 3.0 of the core. It has gone undetected until now, probably because the parameter combination listed above is rare.

In the netlist simulation, the output pipeline registers stall when WE is set to 1 if "Write Mode" is set to "No Read On Write". According to the specifications, this is the correct behavior. However, in both Verilog and VHDL behavioral models, the output pipeline registers always update. If a READ operation was performed on the previous clock cycle, the input value to the pipeline stage will be updated, so that during the write operation, if the output pipeline registers are updated, the DOUT value will be incorrect.

If you have set "Additional Output Pipe Stages" to 1 and "Write Mode" to "No Read On Write", please perform the netlist (gate-level) simulation instead of behavioral simulation. Please see (Xilinx Answer 8065) for information on performing gate-level simulation.
AR# 16129
Date Created 09/03/2007
Last Updated 07/28/2010
Status Archive
Type General Article