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AR# 16147

5.1i Timing Simulation, NGDAnno, Speed Files, MGT - A period error is reported on a REFCLK input

Description

Keywords: timing, simulation, MGT, rocket, I/O, IO, period, $period, REFCLK, 17778, X_GT, Virtex-II Pro

Urgency: Standard

General Description:
When I simulate an MGT in Verilog, the following error occurs:

"# ** Error: C:/Xilinx/verilog/src/simprims/X_GT.v(1316): $period( posedge REFCLK:1992085 ps, :2008085 ps, 17778 ps );
# Time: 2008085 ps Iteration: 1 Instance: /testbench/UUT/u4 "

This error indicates that the minimum period of 17.778 ns for the REFCLK input has been violated.

This error may be invalid, as the speed files have not yet been updated with the minimum period values specified in the data sheet. A -5 speed grade can run at 2.0 Gbps in a FG or BG package, and a -6 or -7 speed grade can run at 2.5 Gbps in a FG or BG package. This correlates to a minimum period of 10 ns for -5 and 8 ns for -6 or -7.

Solution

1

If the REFCLK input frequency is outside the range specified in the Databook, then the REFCLK frequency must be changed to a valid value.

If the REFCLK input frequency is within the range specified in the Databook, this error can be safely ignored.

The speed files will be updated with the correct values in the 5.2i software release.

2

To remove the warnings from the simulation, rather than just ignoring them, the only solution at this time is to edit the SDF file. In general, editing the SDF is not recommended, but it can be done in this case if ignoring the warnings is not acceptable. Also, remember that this change must be made each time a new SDF is created.

To change the SDF, find the Instance that is causing the error. In the example error above, the instance name is u4. In the SDF, please locate the following lines:
(CELL (CELLTYPE "X_GT")
(INSTANCE u4)
:
:

Inside this cell, you will find the following:
:
:
(TIMINGCHECK
(PERIOD (posedge REFCLK) (17778:17778:17778))
:
:

If you are using a Virtex-II Pro -5 device, change the min period to 10 ns as shown below:
(TIMINGCHECK
(PERIOD (posedge REFCLK) (10000:10000:10000))

If you are using a Virtex-II Pro -6 or -7 device, change the min period to 8 ns as shown below:
(TIMINGCHECK
(PERIOD (posedge REFCLK) (8000:8000:8000))
AR# 16147
Date Created 11/14/2002
Last Updated 08/11/2005
Status Archive
Type General Article