AR #16152 - 5.1isp2 Timing Simulation, DCM, Verilog - The DCM does not lock in a verilog timing simulation
5.1isp2 Timing Simulation, DCM, Verilog - The DCM does not lock in a verilog timing simulation
| AR# | 16152 |
| Part | SW-Netgen |
| Last Modified | 2008-11-19 00:00:00.0 |
| Status | Archive |
| Keywords | Timing, Simulation, Verilog, DCM, not, lock, pulse, swallow |
Description
Keywords: Timing, Simulation, Verilog, DCM, not, lock, pulse, swallow
Urgency: Standard
General Description:
In a Verilog timing simulation, the DCM may not lock. This could be the result of pulse-swallowing, or the result of simulating without picosecond resolution.
Solution
First, ensure that the design is being simulated with picosecond resolution.If picosecond resolution is being used, the problem is probably the result of pulse-swallowing.
This problem is fixed in the latest 5.1i Service Pack, available at:
http://support.xilinx.com/support/techsup/sw_updates
The first service pack containing the fix is 5.1i Service Pack 3.
Alternatively, refer to (Xilinx Answer 9872) for a methos of working around this issue.