We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

AR# 16166

6.1 EDK/EST/XPS - My processor system is not my top-level design; how do I perform a behavioral simulation?


Keywords: Xilinx Platform Studio, XPS, simulation, behavioral simulation, ModelSim, MicroBlaze, Power PC, PowerPC, PPC

Urgency: Standard

General Description:
I have created a processor system (MicroBlaze or Virtex-II Pro Power PC) using the Embedded Development Kit tools, and I am using it as a sub-module to my FPGA system. In other words, my processor system is not the top-level of my design. How do I perform a behavioral simulation in ModelSim under these circumstances?


Use the following procedure to perform a behavioral simulation on a processor system instantiated as a sub-module in your top-level HDL design:

Before starting XPS, set up the simulation model libraries according to the "Getting Started Guide" (which is located in "$EDK/doc/edk_getstarted.pdf"). Keep track of the location of these files, especially if you specify a path other than the default. If you use ModelSim XE, you need to upgrade to either ModelSim PE or SE to use the nodebug libraries. If you are unable to upgrade, then you can run only timing or structural simulation.

From XPS
1. Select Options -> Project Options. Set the paths for the simulation libraries. The "Behavioral" library will located where they were compiled with "vmap_edk_libs" during the "getting started" instructions. The UniSim/SimPrim libraries will be located wherever they were previously compiled with Compxlib.

Behavioral: C:\EDK\edk_nd_libs
SimPrim: C:\xilinx\simprim
UniSim: C:\xilinx\unisim

2. Because Platform Studio does not truly support this simulation flow, there are a few options that must be set and then set again in order to produce the proper files for this simulation flow.

Even though the MicroBlaze system will not be your top-level HDL, select Options -> Project Options, then select the Hierarchy and Flow tab. Next, select the radio button next to "This is the top level of my design."

3. Select Tools -> Sim Model Generation.

4. Change the project options in the Hierarchy and Flow tab so that "This is a sub-module of my design" is indicated, and the top-level instance name for your processor system is filled in where indicated.

5. Generate the netlists by selecting Tools -> Generate Netlist.

6. Export to Project Navigator by selecting Tools -> Export to ProjNav.

From ISE
1. Open the ".npl" file that was created by XPS.

NOTE: You might wish to copy your working ".vhd" files into a separate directory so that if you export again from XPS, the files are not over-written accidently. This is particularly important if you are modifying the file "system_stub.vhd" that XPS created. You can also rename "system_stub.vhd" so that the other files are overwritten but this file (a top-level wrapper which instantiates "system.vhd") is not.

2. Create a testbench to provide stimulus for the top-level system.

3. In the testbench, include a configuration statement to load the Block RAM memory initialization strings in the "system_init.vhd" file. Place this statement after the final "END" of your testbench. This is very important, as this is how the instructions get loaded into internal memory. This configuration statement must match the entire hierarchy down from the test bench to the BRAM, so close attention must be given to its accuracy.

The following is an example of a configuration statement that would work for a system with these architecture, entity, and configuration names. You might have to change this statement to match your testbench name, your system instantance name, your LMB BRAM instance name, the implementation names, and the depth of your hierarchy.

configuration testbench_conf of testbench is -- configuration <configuration name> of <testbench entity name>
for behavior -- Testbench architecture
for uut : system_stub -- Testbench instance name : system entity name
for IMP -- System architecture
for mb_sys : system -- Processor system instance name : entity name
for IMP -- Processor System Architecture
for all : bram1_wrapper use configuration work.bram1_conf; -- change "bram1" to the name of the BRAM needing initialization
end for;
end for;
end for;
end for;
end for;
end for;
end testbench_conf;

4. You can now create a custom ".do" file to be run by ModelSim, or you can modify the "<system>.do" file in the simulation directory that was created by SimGen.
a. If you choose to modify "<system>.do", it is a good idea to save this file in another directory so that it is not overwritten or deleted when using XPS for "SimGen" and "Clean" operations.
b. If you create a new ".do" file, it is generally a good idea to locate it in a directory other than "simulation" for the same reasons mentioned in 4.a. Also, if you create your own ".do" file, ensure that the commands from "/simulation/system_init.do" are also run prior to attempting to run the customer ".do" file. You can simply add the command "do system_init.do" to your customer ".do" file at the beginning.

5. Add the following to your ".do" file, modifying the paths to these files as necessary:

vcom -93 -work work ../hdl/system.vhd # In hdl directory
vcom -93 -work work ./system_init.vhd # In simulation directory
vcom -93 -work work ../<top_level>.vhd # wherever you created it
vcom -93 -work work ./<testbench_name>.vhd # wherever you created it

vsim -t ps +notimingchecks work.testbench_conf

6. Add any commands for other files or libraries that might need to be compiled to the "system.do" file with the VCom commands similar to Step 5.

7. Either run the ".do" file from the Modelsim console, or follow the steps below.

8. In the Source Window, select the "<testbench_name>.vhd" file.

9. Right-click "Simulate Behavioral VHDL Model" and select "Properties".

10. Set the "Custom Do File" to the "system.do" in your working directory.

11. Uncheck the "Use Automatic Do File."

12. Click "OK".

13. Double-click "Simulate Behavioral VHDL Model" to start the simulation.
AR# 16166
Date Created 11/15/2002
Last Updated 03/05/2006
Status Archive
Type General Article