We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

AR# 16173

7.1i XST - How do I use incremental design for a single file with multiple modules?


Keywords: synthesis, VHDL, Verilog, flow, coded

Urgency: Standard

General Description:
The Incremental Design flow tracks when and which modules have changed, and only re-synthesizes those modules. However, the process assumes that each module is coded in a separate file. How do I use Incremental Design on a single file that contains several modules coded within it?


The Incremental Design process currently bases re-synthesis only on files that have changed. It cannot detect when one module in a single file containing multiple modules has changed. The whole file will be re-synthesized rather than the changed module.
AR# 16173
Date Created 09/03/2007
Last Updated 01/06/2009
Status Archive
Type General Article