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AR# 16176

LogiCORE SPI-4.2 (POS-PHY L4) - Does the SPI-4.2 Core have a required startup (reset) sequence?

Description

Does the PL4 Core have a required startup sequence?

Yes, the PL4 Core does have a required startup sequence. The information below is the startup sequence needed for both functional and timing simulation, as well as for the device operation. The startup sequence assumes that the entire system involving the Sink and Source cores of the SPI4.2 and their corresponding devices on the SPI-4.2 interface are in the startup state together, whether they are in an FPGA device or a non-FPGA device.

This Answer Record contains three separate resolutions applicable to the SPI4.2 Virtex-4 series, the Virtex-II series, and the SPI4.2 Lite Core. Use the appropriate resolution for your version of the SPI4.2 Core.

Solution

Virtex-4/Virtex-5 Series (SPI4.2 v8.3)

Source:

1. Be sure that the core is in disabled state (SrcEn=0) and assert source core reset (Reset_n=0).

2. Assert and release the TDClk DCM Reset (DcmReset_TDClk) and TSClk DCM Reset (DcmReset_TSClk).

This step is applicable only for the master clocking core using global clock distribution.

3. Wait for the SrcClksRdy signal to be asserted.

If you are using the Source core in slave clocking mode and have provided your own clocking module, be sure to wait until all the clocks necessary for SPI4.2 Core are ready to use.

4. Release the Source core reset (Reset_n).

5. Program the Source Calendar (if required).

6. Enable the Source core (SrcEn = 1).

Sink:

1. Assert sink core reset (Reset_n).

2. Disable sink core enable (snkEn=0).

3. Assert and release the RDClk DCM Reset (DcmReset_RDClk).

4. Wait for the SnkClksRdy signal to be asserted.

5. Assert and release IDELAYCTL reset (SnkIdelayCtlRst) if used.

6. De-assert sink core reset (Reset_n).

7. Program the Sink Calendar (if required).

8. Enable the Sink core (SnkEn = 1).

Dynamic Alignment Mode Only:

9. Pulse the PhaseAlignRequest signal High for 2 x the SnkFFClk period (just long enough for PhaseAlignRequest to be recognized).

10. Deassert the PhaseAlignRequest signal.

11. Monitor SnkDPAFailed and SnkOof. If SnkDPAFailed=1 and SnkOof=1, repeat the PhaseAlignRequest.

If "Auto Retry" is Enabled under the DPA Option, it is not necessary to repeat the PhaseAlignRequest (step 10). The core automatically initiates the alignment again each time the alignment fails. Auto Retry does not initiate the Phase Align Request when the core goes out of frame or loses the lock during normal operation. In this case, you must manually initiate the resynchronization.

NOTE: When Dynamic Phase Alignment mode is used and if you have selected "DPA Wait for Training Control" in the customization gui, the DPA alignment will wait for the training pattern before starting the DPA alignment. However, if "DPA Wait for Training Control" has not been selected, the Sink core must be receiving a valid training pattern at the time PhaseAlignRequest is asserted. You must ensure that the Source core is capable of sending a training pattern at the startup and whenever "Sink Core Out of Frame" (SnkOof) has been asserted by the Sink core. For subsequent alignment, after the high-to-low transition of PhaseAlignRequest, wait for at least eight SnkFFClk clocks before monitoring SnkDPAFail.

Virtex-4/Virtex-5 Series (SPI4.2 v8.1/v8.2)

Source:

1. Assert source core reset (Reset_n).

2. Assert and release the TDClk DCM Reset (DcmReset_TDClk) and TSClk DCM Reset (DcmReset_TSClk).

This step is applicable only for the master clocking core using global clock distribution.

3. Wait for the SrcClksRdy signal to be asserted.

If you are using the Source core in slave clocking mode and have provided your own clocking module, be sure to wait until all the clocks necessary for SPI4.2 Core are ready to use.

4. Release the Source core reset (Reset_n).

5. Program the Source Calendar (if required).

6. Enable the Source core (SrcEn = 1).

Sink:

1. Assert Sink core Reset (Reset_n) and assert sink IDELAYCTL reset (SnkIdelayCtlRst) if used (SnkIdelayCtlRst is an optional signal available in v8.2).

2. Assert and release the RDClk DCM Reset (DcmReset_RDClk).

3. Wait for the SnkClksRdy signal to be asserted.

4. Release Sink core Reset (Reset_n) and the sink IDELAYCTL reset (SnkIdelayCtlRst) if used.

5. Program the Sink Calendar (if required).

6. Enable the Sink core (SnkEn = 1).

Dynamic Alignment Mode Only:

7. Pulse the PhaseAlignRequest signal High for 2 x the SnkFFClk period (just long enough for PhaseAlignRequest to be recognized); deassert the PhaseAlignRequest signal, and monitor SnkDPAFailed and SnkOof. If SnkDPAFailed=1 and SnkOof=1, repeat the PhaseAlignRequest.

If "Auto Retry" is Enabled under the DPA Option, it is not necessary to repeat the PhaseAlignRequest. The core automatically initiates the alignment again each time the alignment fails. Auto Retry does not initiate the Phase Align Request when the core goes out of frame or loses the lock during normal operation. In this case, you must manually initiate the resynchronization.

NOTE: When Dynamic Phase Alignment mode is used, the Sink core must be receiving a valid training pattern at the time PhaseAlignRequest is asserted. You must ensure that the Source core is capable of sending a training pattern at the startup and when "Sink Core Out of Frame" (SnkOof) has been asserted by the Sink core. For subsequent alignment, after the high-to-low transition of PhaseAlignRequest, wait for at least eight SnkFFClk clocks before monitoring SnkDPAFail.

Virtex-4 Series (SPI4.2 v7.4)

Source:

1. Assert source core reset (Reset_n).

This step is applicable only for the master clocking core using global clock distribution.

2. Assert and release the TDClk DCM Reset (DcmReset_TDClk) and TSClk DCM Reset (DcmReset_TSClk).

3. Wait for the SrcClksRdy signal to be asserted.

If you are using the Source core in slave clocking mode and have provided your own clocking module, be sure to wait until all the clocks necessary for the SPI4.2 Core are ready to use.

4. Release the Source core reset (Reset_n).

5. Program the Source Calendar (if required).

6. Enable the Source core (SrcEn = 1).

Sink:

1. Assert sink core reset (Reset_n).

2. Assert and release the RDClk DCM Reset (DcmReset_RDClk).

3. Wait for the SnkClksRdy signal to be asserted.

4. Release the Sink core reset (Reset_n).

5. Program the Sink Calendar (if required).

6. Enable the Sink core (SnkEn = 1).

Dynamic Alignment Mode Only:

7. Wait for 5 us (micro seconds) or instantiate additional IDELAYCTL in the design and wait for a Ready signal from IDELAYCTL.

NOTE: Step 7 is not needed if you have installed the SPI-4.2 v7.4 patch. See (Xilinx Answer 23155).

8. Pulse the PhaseAlignRequest signal High for 2 x the SnkFFClk period (just long enough for PhaseAlignRequest to be recognized), deassert the PhaseAlignRequest signal and monitor SnkDPAFailed and SnkOof. If SnkDPAFailed=1 and SnkOof=1, repeat the PhaseAlignRequest.

NOTE: When Dynamic Phase Alignment mode is used, the Sink core must be receiving a valid training pattern at the time PhaseAlignRequest is asserted. You must ensure that the Source core is capable of sending a training pattern at the startup and when "Sink Core Out of Frame" (SnkOof) has been asserted by the Sink core. For subsequent alignment, after the high-to-low transition of PhaseAlignRequest, wait for at least eight SnkFFClk clocks before monitoring SnkDPAFail.

Virtex-4 Series (SPI4.2 v7.3)

Source:

1. Disable the Source core (SrcEn = 0).

2. Assert and release the TDClk DCM Reset (DcmReset_TDClk) and TSClk DCM Reset (DcmReset_TSClk).

3. Wait for the SrcClksRdy signal to be asserted.

If you are using the Source core in slave clocking mode and have provided your own clocking module, be sure to wait until all the clocks necessary for the SPI4.2 Core are ready to use.

4. Assert the Source core reset (Reset_n).

5. Program the Source Calendar (if required).

6. Enable the Source core (SrcEn = 1).

Sink:

1. Disable the Sink core (SnkEn = 0).

2. Assert and release the RDClk DCM Reset (DcmReset_RDClk).

3. Wait for the SnkClksRdy signal to be asserted.

4. Assert the Sink core reset (Reset_n).

5. Wait until a valid training pattern is available on the SPI-4.2 bus.

6. Release the Sink core reset (Reset_n).

7. Program the Sink Calendar (if required).

8. Enable the Sink core (SnkEn = 1).

Dynamic Alignment Mode Only:

Pulse the PhaseAlignRequest signal High for 2 x the SnkFFClk period (just long enough for PhaseAlignRequest to be recognized), deassert the PhaseAlignRequest signal and wait for PhaseAlignComplete to be asserted. If PhaseAlignComplete is not asserted within 200 clock cycles (SnkFFClk), repeat the PhaseAlignRequest.

NOTE: When Dynamic Phase Alignment mode is used, the Sink core must be receiving a valid training pattern at the time the core Reset_n is being released. You must ensure that the Source core is capable of sending a training pattern at the startup and when "Sink Core Out of Frame" (SnkOof) has been asserted by the Sink core. The training pattern must be ready on the SPI-4.2 bus at the time you release the Sink core reset.

Virtex-4 Series (SPI4.2 v7.2 or v7.1)

Source:

1. Disable the Source core (SrcEn = 0).

2. Assert and release the TDClk DCM Reset (DcmReset_TDClk) and TSClk DCM Reset (DcmReset_TSClk).

3. Wait for the SrcClksRdy signal to be asserted.

If you are using v7.1 or an earlier core using global clocking mode, wait until both the Locked_TDClk and Locked_TSClk are asserted.

If you are using v7.1 or an earlier core using regional clocking mode, wait until SysClkDiv_GP and TSClk_GP start toggling.

If you are using a Source core in slave clocking mode and have provided your own clocking module, be sure to wait until all the clocks necessary for the SPI4.2 Core are ready to use.

4. Assert and release the Source core reset (Reset_n).

5. Program the Source Calendar (if required).

6. Enable the Source core (SrcEn = 1).

Sink:

1. Disable the Sink core (SnkEn = 0).

2. Assert and release the RDClk DCM Reset (DcmReset_RDClk).

3. Wait for the SnkClksRdy signal to be asserted.

If you are using v7.1 or an earlier core using global clocking mode, wait until the RDClk DCM Locked signal (Locked_RDClk) is asserted.

If you are using v7.1 or an earlier core using regional clocking mode, wait until RDClkDiv_GP starts toggling.

4. Assert and release the Sink core reset (Reset_n).

5. Program the Sink Calendar (if required).

6. Enable the Sink core (SnkEn = 1).

7. Dynamic Alignment Mode Only: Pulse the PhaseAlignRequest signal High for 2 x the SnkFFClk period (just long enough for PhaseAlignRequest to be recognized); deassert the PhaseAlignRequest signal and wait for PhaseAlignComplete to be asserted. If PhaseAlignComplete is not asserted within 200 clock cycles (SnkFFClk), repeat the PhaseAlignRequest.

NOTE: When Dynamic Phase Alignment mode is used, the Sink core must be receiving a valid training pattern at the time core Reset_n is being released. You must ensure that the Source core is capable of sending a training pattern at the startup and when "Sink Core Out of Frame" (SnkOof) has been asserted by the Sink core. The valid training pattern must be ready on the SPI-4.2 bus at the time you release the Sink core reset.

Virtex-II and Virtex-II Pro Series (SPI4.2 v6.x)

Source:

1. Disable the Source core (SrcEn = 0).

2. Assert and release the TDClk DCM Reset (DcmReset_TDClk), and wait until the TDClk DCM Locked signal (Locked_TDClk) is asserted.

3. Assert and release the TSClk DCM Reset (DcmReset_TSClk) and wait until the TSClk DCM Locked signal (Locked_TSClk) is asserted.

If you are using a Source core in slave clocking mode and have provided your own clocking module, wait until all the clocks necessary for the SPI4.2 Core are ready to use.

4. Assert and release the Source core reset (Reset_n).

5. Program the Source Calendar (if required).

6. Enable the Source core (SrcEn = 1).

Sink:

1. Disable the Sink core (SnkEn = 0).

2. Assert and release the RDClk DCM Reset (DcmReset_RDClk), and wait until the RDClk DCM Locked signal (Locked_RDClk) is asserted.

3. Assert and release the Sink core reset (Reset_n).

4. Program the Sink Calendar (if required).

5. Enable the Sink core (SnkEn = 1).

6. Dynamic Alignment Mode Only: Pulse the PhaseAlignRequest signal High for 2 x the SnkFFClk period (just long enough for PhaseAlignRequest to be recognized); deassert the PhaseAlignRequest signal, and wait for PhaseAlignComplete to be asserted. Repeat PhaseAlignRequest assertion only if the Sink core goes out of frame during the operation (SnkOof = 1).

NOTE: When Dynamic Phase Alignment mode is used, the Sink core must be receiving a training pattern in order to perform the phase alignment (PhaseAlignRequest). You must ensure that the Source core is capable of sending a training pattern at the startup and when "Sink Core Out of Frame" (SnkOof) has been asserted by the Sink core.

SPI4.2 Lite Core

Source:

1. Disable the Source core (SrcEn = 0).

2. Assert and release the TDClk DCM Reset (DcmReset_TDClk) and wait until the TDClk DCM Locked signal (Locked_TDClk) is asserted.

3. Wait for TSClk_GP to start toggling.

If you are using a Source core in slave clocking mode and have provided your own clocking module, be sure to wait until all the clocks necessary for the SPI4.2 Core are ready to use.

4. Assert and release the Source core reset (Reset_n).

5. Program the Source Calendar (if required).

6. Enable the Source core (SrcEn = 1).

Sink:

1. Disable the Sink core (SnkEn = 0).

2. Assert and release the RDClk DCM Reset (DcmReset_RDClk) and wait until the RDClk DCM Locked signal (Locked_RDClk) is asserted.

If the user clocking module is used, the locked signal from DCM is called Locked_RDClk_USER. If you have provided your own clocking module, wait until all the clocks necessary for the SPI4.2 Core are ready to use.

3. Assert and release the Sink core reset (Reset_n).

4. Program the Sink Calendar (if required).

5. Enable the Sink core (SnkEn = 1).

AR# 16176
Date Created 09/03/2007
Last Updated 12/15/2012
Status Active
Type General Article