AR #16178 - 5.1isp2 Timing Simulation, NGDAnno, Virtex-E - Timing Simulation does not fail when the max clock frequency reported by TRCE is exceeded
5.1isp2 Timing Simulation, NGDAnno, Virtex-E - Timing Simulation does not fail when the max clock frequency reported by TRCE is exceeded
| AR# | 16178 |
| Part | ngdanno |
| Last Modified | 2005-08-11 00:00:00.0 |
| Status | Archive |
| Keywords | Timing, Simulation, NGDAnno, SDF, Virtex-E, clock, skew, setup, max, frequency |
Description
Keywords: Timing, Simulation, NGDAnno, SDF, Virtex-E, clock, skew, setup, max, frequency
Urgency: Standard
General Description:
In some cases, the clock delays in the SDF do not match the delays reported by TRCE. There is a difference in how TRCE and NGDAnno use the speed files, causing a large positive clock skew to be added between two registers. This makes the simulation much more optimistic than TRCE, which allows the simulation to be run with higher clock frequencies than what TRCE reports.
TRCE does not currently report positive clock skew, so the simulation will always be a little more optimistic than the TRCE report, but this difference makes the simulation much more optimistic. The positive clock skew can be as much as 500 ps.
Solution
This problem is fixed in the latest 5.1i Service Pack available at:http://support.xilinx.com/support/techsup/sw_updates
The first service pack containing the fix is 5.1i Service Pack 3.
A certain amount of positive clock skew will still appear in the simulation netlist, but it should be on the order of 100 ps, as it is inside the device.