We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

AR# 16178

5.1isp2 Timing Simulation, NGDAnno, Virtex-E - Timing Simulation does not fail when the max clock frequency reported by TRCE is exceeded


Keywords: Timing, Simulation, NGDAnno, SDF, Virtex-E, clock, skew, setup, max, frequency

Urgency: Standard

General Description:
In some cases, the clock delays in the SDF do not match the delays reported by TRCE. There is a difference in how TRCE and NGDAnno use the speed files, causing a large positive clock skew to be added between two registers. This makes the simulation much more optimistic than TRCE, which allows the simulation to be run with higher clock frequencies than what TRCE reports.

TRCE does not currently report positive clock skew, so the simulation will always be a little more optimistic than the TRCE report, but this difference makes the simulation much more optimistic. The positive clock skew can be as much as 500 ps.


This problem is fixed in the latest 5.1i Service Pack available at:
The first service pack containing the fix is 5.1i Service Pack 3.

A certain amount of positive clock skew will still appear in the simulation netlist, but it should be on the order of 100 ps, as it is inside the device.
AR# 16178
Date Created 11/18/2002
Last Updated 08/11/2005
Status Archive
Type General Article