General Description: Although I selected "LVDS Status Channel I/O" in the PL4 Core GUI, the .ucf file contains pin constraints for LVTTL Status Channel I/O.
In the PL4 v5.0 core, CORE Generator does not automatically adjust the .ucf for LVDS Status Channel I/O. If you have selected LVDS for the status channel, you must manually edit the .ucf file (component_name_pl4_wrapper.ucf).
Modify the following status channel I/O as follows:
- Change "RSClk" to "RSClk_P".
- Add PIN LOC constraints for RStat_P(0) and RStat_P(1)
- Change "TSClk" to "TSClk_P".
- Add PIN LOC constraints for TStat_P(0) and TStat_P(1).
The default LVTTL I/O pin assignments for the status channel output from CORE Generator may need modification in order to support LVDS I/O. For example, the 2v3000-FF1152 constraints file could be updated as follows:
NET "RSClk" LOC = "J27"; ## Other placement may be possible
NET "RSClk_P" LOC = "K27"; ## Other placement may be possible
NET "TSClk" LOC = "AF17";
NET "TSClk_P" LOC = "AG17";
NOTE: There are no specific requirements for the status channel I/O placement; however, Xilinx recommends that the placement of the status channel I/O be constrained to the same bank as the corresponding data I/O.
Adjustment of the UCF will take place automatically in the v6.0 release of SPI 4.2.