Do Xilinx devices support Built-In Self Test (BIST) capability?
Xilinx does not provide any automated BIST functionality, but a user can add BIST to a design. However, most users do not include BIST functionality because the primary reasons for including BIST are addressed by other FPGA design capabilities:
1. I want a simple general test to indicate that the FPGA is working.
This test is easily accomplished by performing any basic JTAG operation (for example, scanning the IDCODE). Programming the part is another good general test.
2. I wish to rigorously test the FPGA or CPLD infrastructure (LUTs, registers, interconnect, etc.)
Xilinx tests the physical components on the die to the greatest extent possible with automatic testing equipment before parts are shipped to customers. The inclusion of a built-in test to check every device resource, in enough combinations to provide adequate coverage, would require an extremely large amount of logic.
3. How do I ensure that my design does what I want it to do?
There is no way for the device or the software to know what the design's function is. The best way to answer this question is to simulate the design in software. ChipScope can be used to compare the actual behavior in hardware, but the user must still know exactly what results are expected.
BIST is primarily used by ASIC designers who do not have the luxury of being able to easily modify the design or insert ChipScope cores. The BIST pattern is included in the design, and it is enabled by a JTAG instruction. The pattern is driven into the inputs, and the outputs are then checked for the correct behavior.
FPGA or CPLD designers can easily add BIST capability to designs, but it may be difficult to justify the additional device resources needed to include BIST.