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AR# 16241

7.1i XST - Known Issues for the mixed language flow

Description

Keywords: VHDL, Verilog

Urgency: Standard

General Description:
The mixed language flow for XST is new with the release of the 6.1i design tools. This Answer provides the Known Issues for this flow:

Known Issues
- Module/entity names in declaration and instantiation are case-sensitive. If the name does not match the case of the module/entity, XST creates a black box for the instantiation and does not connect the underlying module/entity.

- VHDL entities instantiated inside Verilog modules are not found if they are not synthesized into the default work library. This problem has been fixed in the latest 6.1i Service Pack, available at:
http://support.xilinx.com/support/techsup/sw_updates
The first service pack containing the fix is 6.1i Service Pack 1.

- XST generates an internal error if a VHDL entity is instantiated inside of a Verilog generate construct. This problem has been fixed in the latest 6.1i Service Pack, available at:
http://support.xilinx.com/support/techsup/sw_updates
The first service pack containing the fix is 6.1i Service Pack 1.

- VHDL ports with extended identifiers do not connect to lower-level Verilog modules.

- A generic/parameter must be passed even if a default value exists. A VHDL architecture that instantiates a Verilog module must have generics declared in the component declaration if parameters exist in the Verilog module.

- Strings cannot be passed from generics to parameters.

- VHDL configurations are not supported when they reference Verilog modules.

- Multi-dimensional arrays are not supported during instantiations.

Solution

Please refer to the XST User Guide at:
http://support.xilinx.com/support/software_manuals.htm

for the latest information on mixed language flow support
AR# 16241
Date Created 11/25/2002
Last Updated 10/20/2005
Status Archive
Type General Article