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AR# 16282

2.3 System Generator for DSP - Can multiple master System Generator tokens be present in a design?

Description

General Description:  

Can multiple versions of the master System Generator token be present in a design? (This would allow multiple FPGA implementation.)

Solution

Yes -- to enable multiple FPGA implementation: 

 

- Generate the top level of the design. No Xilinx components and/or System Generator tokens should be present in the top level. 

 

- Create the subsystems. (Remember that the FPGA name is derived from the file name and the name of the subsystem.) 

 

- For each subsystem, generate the design normally. Each subsystem will include GatewayIn, GatewayOut, and the System Generator token, which will be the master.  

 

- For the generation of each subsystem, select the System Generator token, select the relevant family, and process as normal.  

 

Example

 

The following example is derived from the Digital Down Converter that is included in the demos. The single 2V3000 device solution (98% full) has been changed to a potentially lower cost three-FPGA implementation consisting of a 2V2000 device (79%) and two low-cost Spartan-IIE 2S300 devices (87%). The Spartan-IIE devices are used for the mixer and I or Q channel of the Digital Down Converter, and the 2V2000 device is used for the second stage polyphase filter. 

 

Digital Down Converter Multiple FPGA solution
Digital Down Converter Multiple FPGA solution
 

 

The mixer, CIC, and filter for the I and Q channels are illustrated below with the System Generator token: 

Mixer Channel
Mixer Channel
 

 

The second stage polyphase filter implementation is as follows: 

Second Polyphase Filter
Second Polyphase Filter

AR# 16282
Date Created 09/03/2007
Last Updated 05/15/2014
Status Archive
Type General Article