We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

AR# 16324

Virtex-II Pro PowerPC - What are the clocks for I-side or D-side of on-chip memory (OCM) for a PowerPC?


General Description:

What are the clocks for I-side or D-side of OCM memory for a PowerPC processor? How do I choose an OCM clock rate?


The OCM clocks must be a ratio of the CPU clock:

- Single-cycle mode access -- OCM Clock : CPU Clock = 1:1.

- Multi-cycle mode -- OCM Clock : CPU Clock = 1:N (in frequency), where N=1, 2, 3, 4 can be set dynamically through application firmware via a DCR write to DSCNTL/ISCNTL registers. You can also set a fixed value by hardwiring DSCNTLVALUE/ISCNTLVALUE PPC ports in the FPGA fabric.

Notice that the I-side OCM and D-side OCM clocks are independent. The rising edges of these OCM clocks must align with the CPU clock's rising edge.

To determine the appropriate ratio:

1. Determine the OCM size (i.e., numbers of BRAMs).

2. Run a timing report of the worst read/write access to this on-chip memory (the BRAM block).

3. Compare the worst-case timing with the CPU's clock period, and find the best ratio that can tolerate the worst case from Step 2.

4. Set up the ratio via the DCR write to DSCNTL/ISCNTL registers (or set a fixed value by hardwiring the DSCNTLVALUE/ISCNTLVALUE PPC ports in the FPGA fabric.

Further steps are needed in order to use DCM correctly. Please refer to:

- The "PowerPC 405 OCM Controller" chapter of the PowerPC 405 Processor Block Reference Guide

- The "Memory-System Management" chapter of the PowerPC Processor Reference Guide

- The Xilinx application note "PLB vs. OCM Comparison using the Packet Processor Software" (Xilinx XAPP644)

AR# 16324
Date Created 09/03/2007
Last Updated 12/15/2012
Status Active
Type General Article