This Answer Record contains a list of all known issues for the SPI-4.2 PL4, also known as POS-PHY Level 4 (PL4) v3.x.
1. When timing simulation is run using the Verilog Demo testbench with the PL4 core, some simulators (such as Verilog-XL) will display incorrect outputs. No errors are reported by the simulator, but the displayed outputs are incorrect.
Please see (Xilinx Answer 11560).
2. When timing simulation is run using the VHDL Demo testbench with the PL4 core, the simulation does not work.
Please see (Xilinx Answer 12422).
3. The PL4 clock requires twelve clock buffers: six clocks and six additional clock inputs (SrcFFWClk, SnkFFRClk, RCalClk, TCalClk, TStatClk, and RStatClk.) What methods are recommended for reducing clock buffer usage?
Please see (Xilinx Answer 12514).
4. POS PHY L4 - The Sink side of a PL4 core does not operate at the given data sheet speed, or else requires that the PHASE_SHIFT setting be significantly different from the 64 default to operate at speed.
Please see (Xilinx Answer 12907).