We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

AR# 16387

5.2i Timing - The timing report data sheet contains incorrect clock edge information


General Description:

The clock edge listed in the data sheet section of the timing report is incorrect for Dual-Data Rate or two opposite-edge registered outputs.


The plurality of the paths covered is the opposite of what it should be.

This will be fixed in the next major software release after 6.1i.

AR# 16387
Date Created 09/03/2007
Last Updated 01/18/2010
Status Archive
Type General Article