After the PROGRAM_B pin is pulled Low, the INIT_B pin is not also pulled Low.
During configuration, INIT_B is pulled Low internally by the FPGA when PROGRAM_B is pulled Low. After the FPGA has initialized, the INIT_B pin is released by the FPGA and configuration may begin.
If the PWRDWN_B pin (_B denoting active Low) is held Low, the FPGA will not pull INIT_B Low when PROGRAM_B is pulled Low, and the FPGA will not configure.
Ensure that PWRDWN_B is not being held Low externally, and be sure that the BitGen "PowerdownPin" option is set to "Pull-up" (it is set to "Pull-up" by default). You can verify this option in the BitGen report (.bgn).
For more information on the PWRDWN pin, please see (Xilinx Answer 12763).