Can clocks be shared between multiple instances of the RapidIO core?
As of the v1.3 release of the Xilinx RapidIO Physical Layer, the transmit clocks may be shared by two or more instances of the core. In the v1.3 release of the core, transmit clock generation was pulled out of the core, allowing user access.
A design example called "tx_clocking.v" illustrates the creation of TX_250, TX_250I, and TX_62. The advantage of this method is that multiple RapidIO cores can be instantiated in a single device and can share valuable transmit clock resources.
The receive clocks cannot be shared by different instances of the core. The Physical Layer uses the 250 MHz RapidIO receive clock (RIO_RCLK) to derive the 62.5 MHz LNK_RCLK supplied to the user application. Each core interface must receive its respective RIO_RCLK and pass a 62.5 LNK_RCLK to the user. The LNK_RCLKs cannot be shared by different instances of the cores.
For more information, please see Chapter 3 of the LogiCORE RapidIO 8-bit Physical Layer Interface Design Guide v1.3. The Design Guide is included with the product zip file in the Physical Layer documentation directory; it is also available on the Xilinx web site at: