We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

AR# 16508

5.1i XST - "FATAL_ERROR:HDLParsers:vhptype.c:172:$Id: vhptype.c,v"


Keywords : HDLParsers, XST, error, aggregate, alias

Urgency: Standard

General Description:
XST reports the following error when I use it to synthesize a VHDL design:

"Compiling vhdl file <filename>.vhd in Library work.
FATAL_ERROR:HDLParsers:vhptype.c:172:$Id: vhptype.c,v 1.6 2001/10/12 21:32:28 weilin Exp $:200 - INTERNAL ERROR... while parsing D:/customer/bastinaire/testcase.vhd line 33. Contact your hot line. Process will terminate. To resolve this error, please consult the Answers Database and other online resources at http://support.xilinx.com. If you need further assistance, please open a Webcase by clicking on the "WebCase" link at http://support.xilinx.com
Error: XST failed
Reason: "

This error has been observed using alias signals in an aggregated assignment:

alias d0 : std_logic is di0;
alias d1 : std_logic is di1;
alias d2 : std_logic is di2;
alias d3 : std_logic is di3;
alias d4 : std_logic is di4;
alias d5 : std_logic is di5;
alias d6 : std_logic is di6;
alias d7 : std_logic is di7;
signal data_l : std_logic_vector(7 downto 0);


The current resolution for this error is to assign the signal using the net names, rather than aliases.

This problem is fixed in the latest 5.2i Service Pack available at:
The first service pack containing the fix is 5.2i Service Pack 2.
AR# 16508
Date Created 01/15/2003
Last Updated 10/20/2005
Status Archive
Type General Article