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AR# 16537

LogiCORE SPI-4.2 (POS-PHY L4) v6.0 - Can I run a PL4 Core in static alignment mode at 700 Mbps using a -5 speed (or at 640 Mbps using a -4 speed)?

Description

General Description: 

Can a PL4 Core in static alignment mode run at 700 Mbps using a -5 speed, or at 640 Mbps using a -4 speed?

Solution

Although the CORE Generator POS PHY Level-4 GUI might not present a specific option for selecting your desired performance, it is possible to modify the UCF to the needed speed. For example, when you select Static Alignment for the configuration, the performance automatically defaults to 800 Mbps and does not allow you to select 700 Mbps. Although the GUI does not present the option to select 700 Mbps, the core can still be run at 700 Mbps. 

 

For an SPI-4.2 (PL4) v5.x Core in Static Alignment Mode, the following device/package combinations can be run at 700 Mbps using a -5 speed device: 

 

XC2V3000-5-FF1152 

XC2V4000-5-FF1152 

XC2V6000-5-FF1152 

XC2V2000-5-BF957 

XC2V3000-5-BF957 

XC2V4000-5-BF957 

XC2V6000-5-BF957 

 

For an SPI-4.2 (PL4) v5.x Core in Static Alignment Mode, the following device/package combinations can be run at 640 Mbps using a -4 speed device:  

 

XC2V2000-4-FG676 

XC2V3000-4-FG676 

 

For an SPI-4.2 (PL4) v5.x Core in Static Alignment Mode targeting a Virtex-II Pro device, the following packages can be run at 640 Mbps using a -5 speed device: 

 

XC2VP20-5-FF1152 

XC2VP50-5-FF1152 

 

NOTE: Because the CORE Generator POS PHY Level-4 GUI does not yet include an option to generate Virtex-II Pro files, the Virtex-II Pro netlists and UCF files are provided through PL4 patch files. Please follow the instructions in the "Readme.txt" included with the respective patch archive, then edit the UCF to include the desired speed. 

 

For example

 

1. In CORE Generator, generate the SPI-4.2 (PL4) Core with static alignment and with 800 Mbps (default).  

 

2. Open the generated UCF using a text editor. The UCF name will be:  

<component_name>_pl4_wrapper.ucf.  

 

3. Edit the following two lines in the UCF:  

 

TIMESPEC "TS_RDClk_P" = PERIOD "RDClk_P" 400 MHz HIGH 50 %;  

 

TIMESPEC "TS_SysClk_P" = PERIOD "SysClk_P" 400 MHz HIGH 50 %;  

 

In both lines above, change "400 MHz" to "350 MHz" for 700 Mbps performance, or "350 MHz" to "320 MHz" for 640 Mbps performance. 

 

4. Use the modified UCF when you run the design through the ISE implementation tool.  

 

NOTE: The GUI will be updated to support all capable performances in a future release of the SPI-4.2 (PL4) Core.

AR# 16537
Date Created 09/03/2007
Last Updated 05/15/2014
Status Archive
Type General Article