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AR# 16548

LogiCORE SPI-4.2 (POS-PHY L4) v5.2 and v5.2.3 (patch) - Release Notes (PL4 Customers Only)


General Description

This Answer Record contains release notes for POS-PHY Level 4 version 5.2 (also known as pl4_v5_2 and pl4_v5_2_3 [patch]), which was released in conjunction with v5.2. The list is divided into the following sections:

- Software Requirements

- Features Available in PL4 v5.2

- Features Available in PL4 v5.2.3 [patch]

- Supported Device/Package Information

- Known Issues


Software Requirements:

SPI-4.2 v5.2 is compatible with:

- Xilinx CORE Generator 5.2i (which is included with the ISE 5.2i software), or

- Xilinx CORE Generator 5.1i (which is included with the ISE 5.1i software) with Service Pack 3 and IP Update #1

Do not install pl4_v5_2 on the ISE 4.2i software.

If you are using ISE 5.1i, the recommended software installation order is as follows:

1. ISE 5.1i CD

2. ISE 5.1i Service Pack 3, which is available at: http://support.xilinx.com/xlnx/xil_sw_updates_home.jsp
3. 5.1i IP Update #1 (also known as F_IP1) at: http://www.support.xilinx.com/ipcenter/coregen/updates_51i.htm
4. pl4_v5_2, which is available only to PL4 customers at: http://www.xilinx.com/ipcenter/posphyl4/posphyl4.htm
5. Apply the pl4_v5_2_3 patch if needed.

NOTE: The files provided in pl4_v5_2_3 (patch) are to be used in conjunction with pl4_v5_2 files. Replace the files as instructed in the provided "readme.txt" only as needed. Using this patch might require you to upgrade to ISE 5.2i. The pl4_v5_2_3 (patch) is available (for PL4 customers only) at: http://www.xilinx.com/ipcenter/posphyl4/posphyl4.htm

Features Available in PL4 v5.2:

1. Full support for ISE 5.1i and ISE 5.2i

2. - The minimum value for "Sink FIFO Threshold Assert" has changed from 4 to 6.

- The minimum value for "Sink FIFO Threshold Negate" has changed from 4 to 6.

- The minimum value for "Source FIFO Threshold Assert" has changed from 4 to 6.

- The minimum value for "Source FIFO Threshold Negate" has changed from 4 to 6.

3. A TSClk synchronization issue has been fixed. Please see (Xilinx Answer 16527) for more information on this issue.

Features Available in PL4 v5.2.3:

1. Support has been added for the TDClk DCM Bypass feature.

2. Support has been added for XC2V6000-5-FF1152 Dynamic Alignment.

- NOTE: If you are using the pl4_v5_2_2 files, please download pl4_v5_2_3, as it will fix the issue mentioned in (Xilinx Answer 16950).

3. Support has been added for Virtex-II Pro devices.

- Virtex-II Pro constraints have been modified so that the status bits are not locked (except TSClk) and default to LVTTL.

- Please see (Xilinx Answer 16777) for information on recommended I/O locking.

- If you are using LVTTL status, you must use the 5.2i software.

- If you are using LVDS status, you may use the 5.1i Service Pack 3 software.

Supported Device and Package Information:

PL4 v5.2 and v5.2.3 (patch) supports the Device and Package combinations listed at:


Known Issues:

Please see (Xilinx Answer 12420) for a list of PL4 Known Issues.

AR# 16548
Date Created 09/03/2007
Last Updated 05/03/2010
Status Archive
Type General Article