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AR# 16616

10.1 State Diagram Editor - Blocking/Non-blocking statements are not used optimally in Verilog State Machine code

Description

Verilog State Machine code generated by StateCAD might not be optimal.

Below is an example of non-optimal code output from StateCAD:

always @(posedge CLK)

begin

cnt1 = next_cnt1;

end

always @(posedge CLK)

begin

cnt0 = next_cnt0;

end

What this will do is assign

cnt1 = next_cnt1

cnt0 = next_cnt0

on each clock edge, but if non- blocking statements were used, you would need only this:

always @(posedge CLK)

begin

cnt1 <= next_cnt1;

cnt0 <= next_cnt0;

end

Solution

Although the code is not optimal, it is functionally correct and should not lead to performance issues in an actual device. Because of the difficulty and risk involved with fixing this portion of the StateCAD code generator, it was decided to leave this functionality as it is.

Users should be aware that this could possibly lead to a race condition in behavioral simulation. Where multiple processes are used in place of one, the simulator has to decide which one to process first. If an assigned value is dependent on another assigned value in another process, it is possible to get differing simulation results, depending on the order in which the processes are handled.

AR# 16616
Date Created 09/03/2007
Last Updated 12/15/2012
Status Active
Type General Article