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AR# 16638

v2.2 Aurora Reference Design - How do I modify the Aurora Reference Design to operate from 600 Mb/s to 1 Gb/s?


General Description:

COREGen generates Aurora in full-rate mode to operate from 1 Gb/s to 3.125 Gb/s. Modifications have to be made to the generated design to get it to operate at the lower rates.


The steps below outline how to complete the modification:

1. Change MGT instantiation in generated design to Half-rate mode:

Change the SERDES_10B attribute for each lane to TRUE.

2. For a 2-byte lane design, MGT input ports RXUSRCLK2 and TXUSRCLK2 must be disconnected from USER_CLK. Add an input port called USER_CLK_N_2X to the port list for the top level of the Aurora module. Connect USER_CLK_N_2X to the RXUSRCLK2 and TXUSRCLK2 ports from each MGT.

For a 4-byte lane design, USER_CLK_N_2X is already connected.

3. Use a DCM to provide the clocks to the USER_CLK and USER_CLK_N_2X ports:

For a 2-byte lane design, USER_CLK must be 1/2 the rate of the reference clock, and USER_CLK_N_2X must be shifted 180 degrees from USER_CLK.

For a 4-byte lane design, create USER_CLK by dividing the reference clock by 2 and shifting it 180 degrees using the CLKFX180 port of a DCM, and USER_CLK_N_2X by dividing the reference clock by 4 using the CLKDV port.

AR# 16638
Date Created 09/03/2007
Last Updated 12/15/2012
Status Active
Type General Article