We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

AR# 16742

6.1i CPLD TAEngine - Timing constraints do not obey the proper FROM:TO location ranges


Keywords: 6.1i, 5.2i, 5.1i , CPLD, TAEngine, timing constraint

Urgency: Hot

General Description:
The CPLD timing analysis tool of the TAEngine does not obey the "From" portion of a FROM:TO constraint. The constraint picks up only the "To" portion and, as a result, covers many more paths than expected.


Because more paths are covered by the constraint than intended, you can work around this issue by inspecting all paths to verify the validity of each path with respect to the starting point indicated in the timing constraint.

This problem has been fixed in the latest 6.1i Service Pack, available at:
The first service pack containing the fix is 6.1i Service Pack 1.
AR# 16742
Date Created 09/03/2007
Last Updated 08/13/2009
Status Archive
Type General Article