We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

AR# 16789

8.1i Schematic - A schematic check reports: "ERROR:DesignEntry:31 - drawing attribute name "Type" is a reserved keyword for VHDL."


Keywords: ECS, symbol, attribute, type, DRC, Verilog

When I run a process on a top-level schematic design, ISE reports the following Design Rule Checking error:

"ERROR:DesignEntry:31 - drawing attribute name "Type" is a reserved keyword for VHDL."


Symbol files created with versions of ISE earlier than version 5.1i might have an attribute named "Type" in the Symbol object properties. In ISE 6.1i and later, the schematic design rule check flags this attribute as a VHDL reserved word. Because of the "Mixed language" capabilities added in ISE 6.1i, a schematic may be checked for both VHDL and Verilog reserved words.

To remove the Type attribute, follow these steps:
1. Open the symbol file in ECS.
2. Select Edit -> Object Properties.
3. Click the "Type" attribute name, and then click the "Delete" button.
4. Save the symbol.

To ignore the use of this VHDL reserved word when running a Verilog-only flow, follow these steps:
1. Open the schematic editor.
2. Select Edit -> Preferences.
3. In the Category window, select "Check" under Symbol Editor.
4. Un-check the option "Check VHDL Reserved Keywords".
AR# 16789
Date Created 03/03/2003
Last Updated 12/12/2006
Status Archive
Type General Article