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AR# 16832

JTAG - What is a JTAG scan bridge, scan path linker, or JTAG multiplexer/JTAG mux?

Description

What is a JTAG scan bridge, also referred to as a scan path linker or JTAG mux? How do they work, what are they used for, and are they supported by Xilinx JTAG software applications and devices?

Solution

Overview

JTAG scan bridges (also referred to as JTAG scan path linkers or JTAG multiplexors) are devices that expand the functionality of the 1149.1 and 1532 IEEE JTAG standards by providing a way to dynamically change the structure of a JTAG chain. For example, if you have a large number of JTAG devices in your design, you can connect them to a JTAG scan bridge and cause portions of the chain to be removed or included by sending instructions to the bridge.

Multiplexing Local Scan Ports (LSPs)

A JTAG scan bridge always has a dedicated "primary" or "backplane" JTAG port, and two or more 'local' or "secondary" scan ports. All JTAG instructions are sent to the scan bridge through the primary JTAG port and multiplexed to either the scan bridge itself or to the secondary scan ports, as follows:



Primary JTAG chain TDI -> Scan Bridge| ----- TDI0 -> Secondary scan chain0---|

Primary JTAG chain TDO <-...................... |<--- TDO0-----------------------------------------|

..............................................................................|

..............................................................................|------TDI1 -> Secondary scan chain1---|

..............................................................................|<--- TDO1-----------------------------------------|

..............................................................................|

..............................................................................|------TDIn -> Secondary scan chain n---|

..............................................................................|<--- TDOn------------------------------------------|



Connected to each of the LSPs is a "secondary" JTAG chain with an arbitrary number of devices, although the length of the secondary JTAG chain is typically only a few devices. By sending an instruction to the scan bridge, you can access each secondary chain individually or connect them in any combination to form a larger secondary JTAG chain.

The JTAG scan bridge is a JTAG device with an Instruction Register (IR) and one or more Data Registers (DRs). Secondary chains are selected and multiplexed together through JTAG instructions that are sent to the scan bridge. Unlike other JTAG devices, the scan bridge's TDO signal does not get passed to a downstream device in the secondary chain. All of its JTAG pins (TDI, TMS, TCK, TRST, and TDO) are only connected to the primary JTAG chain to provide support for multi-drop applications (see below). If secondary JTAG chains are not selected, the scan bridge appears as the only device in the chain.

Most JTAG scan bridges (such as the TI device listed below) also feature a "transparent" mode that allows a direct connection from the primary JTAG port to the secondary JTAG port through a one-bit register. As a result, the secondary JTAG chain appears to the primary JTAG header as the only chain on the board. Note that "transparent" mode is not equivalent to BYPASS, since the connection to the secondary JTAG chain must first be defined by instructions sent to the JTAG mux.

Multi-drop Applications for Scan Bridges

JTAG scan bridges are primarily used to test "multi-drop" applications. A multi-drop application uses a dedicated backplane board with slots for a number of daughter boards, similar to a motherboard inside a PC. Since a traditional JTAG chain is serial, an empty slot breaks the JTAG chain. For example, imagine a JTAG chain on a PC motherboard that connects to each of the PCI slots. To complete the chain, each slot must be filled so that the TDO signal from the upstream device connects to TDI on the downstream device.

To allow for JTAG testing in multi-drop applications, you can use a scan bridge in one of the following two ways:

1. Each of the daughter boards can be a secondary JTAG chain coming from the scan bridge.
2. A separate addressable scan bridge can be placed on each daughter board; the TDI, TMS, TDO, TCK, and TRST signals are sent in parallel to each daughter board.

In the second scenario, each daughter board is designed with the scan bridge's primary JTAG port connected to the five JTAG signals coming from the backplane. All JTAG devices on the daughter board are connected to one or more of the scan bridge's secondary JTAG ports. To access a particular scan bridge, you can send the address of the scan bridge that you want to target over the primary JTAG interface. Each scan bridge is wired with a unique address. If the address that is sent over the primary JTAG interface matches this address, the scan bridge is enabled.

Xilinx tools support support for Scan Bridges

Xilinx tools that use JTAG access (iMPACT, ChipScope, XMD, HW CoSim) do not support JTAG scan bridges directly. We do not design the tools to interact with scan chips or include them in Xilinx testing. However, iMPACT can write SVF or STAPL files that can be used by a third-party Boundary Scan tool (such as Asset-Intertech Scanworks or JTAG Technologies) to send JTAG vectors to the target Xilinx device while handling the scan bridge as necessary. For an individual scan chip it may be possible to set the chip into BYPASS or a "transparent" mode to allow Xilinx tools to work with the csn chain. Xilinx tools use a TMS asserted for 5 TCK cycles to set the JTAG chain to a know state with all devices in TLR. This sequence can be used a reset for some scan chips affecting the chain selected. You shoulc consult your scan chips documentation to establish how it can work with Xilinx tools.

Xilinx Device Support for Scan Bridges

All Xilinx FPGAs, CPLDs, and 18V00/XCF00S PROMs are compatible with third-party scan bridges except the XCF00P PROMs and Virtex-II/-II Pro. Both of these device families are not are not fully compatible with scan chains. The Virtex-II/-II Pro devices do not support the Pause-IR state (Xilinx Answer 15983) The XCF00P PROMs do not support the Pause-IR or Pause-DR state (Xilinx Answer 22539) This is problematic when trying to synchronize separate secondary scan chains. Some scan bridges can work around the Pause-IR or Pause-DR problem by "gating" the TCK signal instead of using the Pause states.

Scan Bridges and System ACE CF

The Xilinx System ACE CF (Compact Flash) In-System Configuration Solution configures target FPGA devices through the FPGA JTAG port. If you want to use System ACE CF in combination with a scan path linker, Xilinx recommends that you place the ACE CF device in the same secondary JTAG chain as the target FPGA devices. System ACE CF does not currently support the instructions necessary to handle a downstream scan path linker (connected to its Configuration JTAG port). The scan path linker should be connected to the ACE CF's Test JTAG port.

Manufacturers of JTAG Scan Bridges

National Semiconductor SCANSTA111 Enhanced Scan Bridge Multi-drop Addressable JTAG Scan Port at:
http://www.national.com/pf/SC/SCANSTA111.html

Technologies JTS03/06 IEEE1149.1 Gateway Device at:
http://www.firecron.com/products/products.htm

Texas Instruments Application Report SCTA056 at:
(search for "Cascading Multiple-Linking Addressable-Scan-Port Devices" from the Home page)
http://www.ti.com/

Intellitech Multi-Drop system at:
http://www.intellitech.com/products/ptc.asp

Intellitech Scan Ring Linker
http://www.intellitech.com/products/srl.asp

Further Reading

Asset -Intertech Design For Testability (DFT) guidelines:

http://www.asset-intertech.com/support/dft_rules.html -> "Guidelines for Board DFT Based on Boundary Scan" (.pdf file)

National SCANSTA111/112 integration with iMPACT:
http://www.national.com/an/AN/AN-1340.pdf
AR# 16832
Date Created 09/03/2007
Last Updated 07/18/2011
Status Active
Type General Article