AR #16861 - 6.3i CPLD TAEngine - Timing Analyzer does not check the duty-cycle portion of the period constraint
6.3i CPLD TAEngine - Timing Analyzer does not check the duty-cycle portion of the period constraint
| AR# | 16861 |
| Topic | taengine |
| Last Modified | 2005-04-04 00:00:00.0 |
| Status | Active |
Description
Keywords: 6.2i, 6.1i, 5.2i, 5.1i, 6.1i, analysis
Urgency: Standard
General Description:
The CPLD Timing Analyzer does not check the duty-cycle portion of a period constraint.
Example:
TIMESPEC "TS_test" = PERIOD "clk" 10 ns HIGH 1 %;
TAEngine reports this constraint as MET, even though Xilinx CPLDs cannot operate a clock input with this duty-cycle.