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AR# 16861

6.3i CPLD TAEngine - Timing Analyzer does not check the duty-cycle portion of the period constraint

Description

General Description: 

The CPLD Timing Analyzer does not check the duty-cycle portion of a period constraint. 

 

Example

 

TIMESPEC "TS_test" = PERIOD "clk" 10 ns HIGH 1 %; 

 

TAEngine reports this constraint as MET, even though Xilinx CPLDs cannot operate a clock input with this duty-cycle.

Solution

This problem is fixed in 7.1i.

AR# 16861
Date Created 09/03/2007
Last Updated 05/08/2014
Status Archive
Type General Article