When the following syntax is used in the MHS file, and the design is NOT the top-level, PlatGen generates an incorrect system.vhd or system.v file, which fails in synthesis or simulation.
PORT leds = leds_s, DIR = INOUT, VEC = [3:0]
The system.vhd/.v file fails to include a signal/wire declaration for "leds_s".
You can easily resolve this issue by using the same port and signal name:
PORT leds = leds , DIR=IO, VEC=[3:0]