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AR# 16996

Vivado/ISE - How does the bitstream compress option work (MFWR - Multiple Frame Write Register)? How much compression will be achieved?

Description

Tool documentation does not clearly describe the bitstream compress option. 

What is the default value? What are the arguments for this command? How does it work? How much compression can it achieve?

Solution

ISE:

Compress:

This option uses the multiple frame write feature in the bitstream to reduce the size of the bitstream, not just the ".bit" file. Using the "compress" option does not guarantee that the size of the bitstream will shrink. 

Compression is enabled by setting the BitGen option "-g compress"; and is disabled by not setting this option.

Note: Partial bit files generated with the BitGen "-r" or "-g Partial Mask" setting automatically use the multiple frame write feature and are "compressed" bitstreams.

For more information, see (Xilinx XAPP290): "Two Flows for Partial Reconfiguration: Module Based or Small Bit Manipulations."


Architectures: Virtex, Virtex-E, Virtex-II, Virtex-II Pro, Spartan-II, Spartan-IIE, Spartan-3

Settings: None

Default: Off


How does BitGen "-g compress" work?

The "-g compress" option works by writing identical configuration frames once instead of writing each frame individually. If more than one frame has identical data, the frame is loaded into the configuration logic and written to multiple address locations with the Multiple Frame Write Register (IMF). 

Depending on the utilization of the device, this might decrease the size of the bitstream considerably. To write multiple frames with the same data, BitGen constructs a bitstream with the following commands:

  1. Write WCFG command to CMD register (WCFG command = write packet data; CMD = Command register).
  2. Write desired frame to FDRI (FDRI = Frame Data Register Input).
  3. Write to FAR register with the first desired address (FAR = Frame Address Register).
  4. Write MFWR command to CMD register.
  5. Write two dummy words to the MFWR register.
  6. Write to FAR register with the second desired address.
  7. Write two dummy words to MFW.
  8. Repeat steps 7 and 8 until the last desired address.


NOTES:

  1. You do not need to be concerned with the details of how a "-g compress" bitstream is constructed; these steps are provided for information purposes only.
  2. For background information on the composition of the Virtex bitstream, refer to (Xilinx XAPP151): "Virtex Series Configuration Architecture User Guide."
    The Virtex-II and Virtex-II Pro bitstreams are similar; specific information on these architectures is available in the "Configuration Details" section of the applicable FPGA User Guide at:


http://www.xilinx.com/xlnx/xweb/xil_publications_index.jsp?category=User+Guides

The configuration registers (CMD, FAR, MFWR, etc.) are explained in these guides.

How much of a reduction in bitstream size will I see with the "-g compress" option?

The "-g compress" option works by writing identical configuration frames once rather than many times. Configuration frames are arranged vertically

As a result, a design that spans the fewest possible number of columns will achieve greater compression than a design that spans across the width of the device.

Identical frames are usually found in block RAM columns that are initialized with identical values, or in unused CLB or block RAM columns. To estimate the amount of compression that will be achieved, follow these steps:


1) Identify the number of identical CLB or block RAM columns. This can be difficult to determine because in most cases CLB columns are identical only if they are unused. 

Block RAM columns are identical if the same initialization values are used for multiple columns of block RAMS.


2) Calculate the number of configuration frames for the column type of interest:

# config frames = (# frames per column) x (# of columns)

The number of frames per column is as follows for Virtex-II:


CLB: 22 frames per column

BRAM: 64 frames per column


To find this information for Virtex, refer to (Xilinx XAPP151): "Virtex Series Configuration Architecture User Guide."

To determine the number of columns, use the FPGA Editor or the Floorplanner. For example, an xc2v40 has two block RAM columns (two columns of two block RAMs for a total of four block RAMs).


3) The number of saved configuration frames is the total number of identical frames (from two) minus one. 


4) Calculate the number of saved configuration bits:

= (# of saved configuration frames) x (# of bits per frame)

The number of bits per frame is provided in the Virtex-II/-II Pro User Guide or in (Xilinx XAPP151).


For Example:

In an xc2v40 design that initializes all block RAM values to zero, how much compression can be achieved by using an MFWR to program these columns?


Number of block RAM columns in a 2v40 (from FPGA Editor): 2

(A 2v40 has four block RAMs arranged in two columns of two block RAMs.)


Number of block RAM configuration frames in a 2v40:

= (64 frames / BRAM column) x (2 BRAM columns) = 128 BRAM configuration frames


Number of block RAM configuration frames that do not need to appear explicitly in the bitstream (i.e., "compressed" frames):

= (128 BRAM config frames) - (1 BRAM config frame) = 127 BRAM configuration frames


Number of configuration bits saved:

= (127 BRAM config frames) x (832 bits per frame (from Table 3-15 in the Virtex-II User Guide))

= 105,664 bits


Size of an uncompressed 2v40 bitstream: 360,096

Approximate compression achieved: 105,664/360,096 = 30%

Note: This value should be considered as an estimate only.


Vivado:

Vivado uses the following bitstream property to enable compression:

set_property BITSTREAM.GENERAL.COMPRESS TRUE [current_design]

The multiple frame write (compression) algorithm explained above applies to Vivado and can be used to estimate compression results for bitstreams generated for newer device families that are supported in Vivado.

AR# 16996
Date Created 04/01/2003
Last Updated 04/27/2016
Status Active
Type General Article
Devices
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